From b5c5371848084f6b8738c3be85267c2cd2c9fbc2 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Tue, 6 Feb 2024 21:58:07 +0100 Subject: [PATCH] Arm64Emitter: Don't optimize ADD to MOV for SP Unlike ADD (immediate), MOV (register) treats SP as ZR. Therefore the ADDI2R optimization that was added in 67791d227c can't optimize ADD to MOV when exactly one of the registers is SP. There currently isn't any code in Dolphin that calls ADDI2R with parameters that would trigger this case. --- Source/Core/Common/Arm64Emitter.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Source/Core/Common/Arm64Emitter.cpp b/Source/Core/Common/Arm64Emitter.cpp index 4dd39c4357..f769edc2f3 100644 --- a/Source/Core/Common/Arm64Emitter.cpp +++ b/Source/Core/Common/Arm64Emitter.cpp @@ -4222,9 +4222,15 @@ void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool nega // Special path for zeroes if (imm == 0 && !flags) { - if (Rd != Rn) + if (Rd == Rn) + { + return; + } + else if (DecodeReg(Rd) != DecodeReg(ARM64Reg::SP) && DecodeReg(Rn) != DecodeReg(ARM64Reg::SP)) + { MOV(Rd, Rn); - return; + return; + } } // Regular fast paths, aarch64 immediate instructions