More clean up + ilrrn
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2908 8ced0084-cf51-0410-be5f-012b33b47a6e
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nakeee
parent
b801e16cd3
commit
a300a37906
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@ -112,15 +112,8 @@ void ret(const UDSPInstruction& opc)
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}
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}
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// FIXME inside
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void rti(const UDSPInstruction& opc)
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{
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if ((opc.hex & 0xf) != 0xf)
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{
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// FIXME: Implement
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ERROR_LOG(DSPLLE, "dsp rti opcode");
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}
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g_dsp.r[DSP_REG_SR] = dsp_reg_load_stack(DSP_STACK_D);
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g_dsp.pc = dsp_reg_load_stack(DSP_STACK_C);
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@ -338,32 +331,59 @@ void srrn(const UDSPInstruction& opc)
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g_dsp.r[dreg] += g_dsp.r[dreg + 4];
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}
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// FIXME inside
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// ILRR $acD.m, @$arS
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// 0000 001d 0001 00ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m.
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void ilrr(const UDSPInstruction& opc)
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{
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u16 reg = opc.hex & 0x3;
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u16 dreg = 0x1e + ((opc.hex >> 8) & 1);
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u16 dreg = DSP_REG_ACM0 + ((opc.hex >> 8) & 1);
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g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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}
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// ILRRD $acD.m, @$arS
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// 0000 001d 0001 01ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m. Decrement addressing register $arS.
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void ilrrd(const UDSPInstruction& opc)
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{
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u16 reg = opc.hex & 0x3;
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u16 dreg = DSP_REG_ACM0 + ((opc.hex >> 8) & 1);
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// always to acc0 ?
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g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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switch ((opc.hex >> 2) & 0x3)
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{
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case 0x0: // no change (ILRR)
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break;
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g_dsp.r[reg]--;
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}
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case 0x1: // post decrement (ILRRD?)
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g_dsp.r[reg]--;
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break;
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// ILRRI $acD.m, @$S
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// 0000 001d 0001 10ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m. Increment addressing register $arS.
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void ilrri(const UDSPInstruction& opc)
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{
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u16 reg = opc.hex & 0x3;
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u16 dreg = DSP_REG_ACM0 + ((opc.hex >> 8) & 1);
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case 0x2: // post increment (ILRRI)
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g_dsp.r[reg]++;
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break;
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g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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default:
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// FIXME: Implement
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ERROR_LOG(DSPLLE, "Unknown ILRR: 0x%04x\n", (opc.hex >> 2) & 0x3);
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}
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g_dsp.r[reg]++;
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}
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// ILRRN $acD.m, @$arS
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// 0000 001d 0001 11ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m. Add corresponding indexing
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// register $ixS to addressing register $arS.
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void ilrrn(const UDSPInstruction& opc)
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{
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u16 reg = opc.hex & 0x3;
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u16 dreg = DSP_REG_ACM0 + ((opc.hex >> 8) & 1);
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g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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g_dsp.r[reg] += g_dsp.r[DSP_REG_IX0 + reg];
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}
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@ -641,7 +661,6 @@ void nx(const UDSPInstruction& opc)
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}
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// FIXME inside
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// Hermes switched andf and andcf, so check to make sure they are still correct
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// ANDCF $acD.m, #I
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// 0000 001r 1100 0000
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@ -650,12 +669,6 @@ void nx(const UDSPInstruction& opc)
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// accumulator mid part $acD.m with immediate value I is equal zero.
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void andfc(const UDSPInstruction& opc)
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{
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if (opc.hex & 0xf)
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{
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// FIXME: Implement
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ERROR_LOG(DSPLLE, "dsp_opc.hex_andfc");
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}
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u8 reg = (opc.hex >> 8) & 0x1;
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u16 imm = dsp_fetch_code();
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u16 val = dsp_get_acc_m(reg);
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@ -670,7 +683,6 @@ void andfc(const UDSPInstruction& opc)
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}
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}
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// FIXME inside
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// Hermes switched andf and andcf, so check to make sure they are still correct
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// ANDF $acD.m, #I
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@ -685,12 +697,6 @@ void andf(const UDSPInstruction& opc)
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u16 imm;
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u16 val;
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if (opc.hex & 0xf)
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{
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// FIXME: Implement
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ERROR_LOG(DSPLLE, "dsp andf opcode");
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}
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reg = 0x1e + ((opc.hex >> 8) & 0x1);
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imm = dsp_fetch_code();
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val = g_dsp.r[reg];
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@ -717,15 +723,8 @@ void cmpi(const UDSPInstruction& opc)
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Update_SR_Register64(res);
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}
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// FIXME inside
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void xori(const UDSPInstruction& opc)
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{
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if (opc.hex & 0xf)
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{
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// FIXME: Implement
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ERROR_LOG(DSPLLE, "dsp xori opcode");
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}
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u8 reg = 0x1e + ((opc.hex >> 8) & 0x1);
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u16 imm = dsp_fetch_code();
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g_dsp.r[reg] ^= imm;
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@ -733,19 +732,12 @@ void xori(const UDSPInstruction& opc)
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Update_SR_Register16((s16)g_dsp.r[reg]);
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}
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//FIXME inside
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// ANDI $acD.m, #I
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// 0000 001r 0100 0000
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// iiii iiii iiii iiii
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// Logic AND of accumulator mid part $acD.m with immediate value I.
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void andi(const UDSPInstruction& opc)
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{
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if (opc.hex & 0xf)
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{
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// FIXME: Implement
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ERROR_LOG(DSPLLE, "dsp andi opcode");
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}
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u8 reg = 0x1e + ((opc.hex >> 8) & 0x1);
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u16 imm = dsp_fetch_code();
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g_dsp.r[reg] &= imm;
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@ -755,17 +747,8 @@ void andi(const UDSPInstruction& opc)
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// F|RES: i am not sure if this shouldnt be the whole ACC
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//
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//FIXME inside
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void ori(const UDSPInstruction& opc)
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{
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if (opc.hex & 0xf)
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{
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// FIXME: Implement
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ERROR_LOG(DSPLLE, "dsp ori opcode");
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return;
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}
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u8 reg = 0x1e + ((opc.hex >> 8) & 0x1);
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u16 imm = dsp_fetch_code();
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g_dsp.r[reg] |= imm;
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@ -1108,7 +1091,7 @@ void lsr(const UDSPInstruction& opc)
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u16 shift = -opc.ushift;
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u64 acc = dsp_get_long_acc(opc.areg);
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// Lop off the extraneous sign extension our 64-bit fake accum causes
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acc &= 0x000000FFFFFFFFFF;
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acc &= 0x000000FFFFFFFFFFULL;
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acc >>= shift;
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dsp_set_long_acc(opc.areg, (s64)acc);
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@ -118,17 +118,20 @@ void srs(const UDSPInstruction& opc);
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void lrs(const UDSPInstruction& opc);
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void nx(const UDSPInstruction& opc);
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void cmpi(const UDSPInstruction& opc);
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// FIXME inside
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void rti(const UDSPInstruction& opc);
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void ilrr(const UDSPInstruction& opc);
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void srbith(const UDSPInstruction& opc);
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void ilrrd(const UDSPInstruction& opc);
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void ilrri(const UDSPInstruction& opc);
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void ilrrn(const UDSPInstruction& opc);
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void andfc(const UDSPInstruction& opc);
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void andf(const UDSPInstruction& opc);
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void xori(const UDSPInstruction& opc);
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void andi(const UDSPInstruction& opc);
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void ori(const UDSPInstruction& opc);
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// FIXME inside
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void srbith(const UDSPInstruction& opc);
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// END OF FIXMEs
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// TODO: PENDING IMPLEMENTATION / UNIMPLEMENTED
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@ -181,8 +181,9 @@ DSPOPCTemplate opcodes[] =
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{"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL},
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{"ILRR", 0x0210, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL},
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{"ILRRD", 0x0214, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL}, // Hermes doesn't list this
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{"ILRRI", 0x0218, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL},
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{"ILRRD", 0x0214, 0xfedc, DSPInterpreter::ilrrd, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL}, // Hermes doesn't list this
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{"ILRRI", 0x0218, 0xfedc, DSPInterpreter::ilrri, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL},
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{"ILRRN", 0x0218, 0xfedc, DSPInterpreter::ilrrn, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL},
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// load and store value pointed by indexing reg and increment; LRR/SRR variants
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{"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
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