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This commit is contained in:
Scott Mansell 2015-04-05 21:18:05 +12:00
parent e9459fb30a
commit 9fdc713c87
1 changed files with 14 additions and 0 deletions
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14
Source/Core/Core/PowerPC/Jit64IL/IR_X86.cpp
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@ -43,8 +43,19 @@ struct RegInfo
JitIL *Jit;
IRBuilder* Build;
InstLoc FirstI;
// IInfo contains (per instruction)
// Bits 0-1: Saturating count of number of instructions referencing this instruction.
// Bits 2-3: single bit per operand marking if this is the last instruction to reference that operand's result.
// Used to decide if we should free any registers associated with the operands after this instruction
// and if we can clobber the operands registers.
// Warning, Memory instruction use these bits slightly differently.
// Bits 15-31: Spill location
std::vector<unsigned> IInfo;
// The last instruction which uses the result of this instruction. Used by the register allocator.
std::vector<InstLoc> lastUsed;
InstLoc regs[MAX_NUMBER_OF_REGS];
InstLoc fregs[MAX_NUMBER_OF_REGS];
unsigned numSpills;
@ -412,6 +423,8 @@ static X64Reg regBinLHSReg(RegInfo& RI, InstLoc I)
return reg;
}
// Clear any registers which end their lifetime at I
// Don't use this for special instructions like memory load/stores
static void regNormalRegClear(RegInfo& RI, InstLoc I)
{
if (RI.IInfo[I - RI.FirstI] & 4)
@ -420,6 +433,7 @@ static void regNormalRegClear(RegInfo& RI, InstLoc I)
regClearInst(RI, getOp2(I));
}
// Clear any floating point registers which end their lifetime at I
static void fregNormalRegClear(RegInfo& RI, InstLoc I)
{
if (RI.IInfo[I - RI.FirstI] & 4)