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[ARM] JitASM miroops. No functionality change.

This commit is contained in:
Ryan Houdek 2013-08-18 17:44:53 +00:00
parent 5782530b40
commit 9f4ca0e0a7
2 changed files with 26 additions and 26 deletions
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23
Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp
View File

@ -51,7 +51,7 @@ void JitArm::Init()
gpr.Init(this); gpr.Init(this);
fpr.Init(this); fpr.Init(this);
jo.enableBlocklink = true; jo.enableBlocklink = true;
jo.optimizeGatherPipe = false; jo.optimizeGatherPipe = true;
} }
void JitArm::ClearCache() void JitArm::ClearCache()
@ -132,7 +132,11 @@ static void ImHere()
void JitArm::Cleanup() void JitArm::Cleanup()
{ {
if (jo.optimizeGatherPipe && js.fifoBytesThisBlock > 0) if (jo.optimizeGatherPipe && js.fifoBytesThisBlock > 0)
{
PUSH(4, R0, R1, R2, R3);
QuickCallFunction(R14, (void*)&GPFifo::CheckGatherPipe); QuickCallFunction(R14, (void*)&GPFifo::CheckGatherPipe);
POP(4, R0, R1, R2, R3);
}
} }
void JitArm::DoDownCount() void JitArm::DoDownCount()
{ {
@ -285,9 +289,9 @@ void STACKALIGN JitArm::Jit(u32 em_address)
ClearCache(); ClearCache();
} }
int block_num = blocks.AllocateBlock(em_address); int block_num = blocks.AllocateBlock(PowerPC::ppcState.pc);
JitBlock *b = blocks.GetBlock(block_num); JitBlock *b = blocks.GetBlock(block_num);
const u8* BlockPtr = DoJit(em_address, &code_buffer, b); const u8* BlockPtr = DoJit(PowerPC::ppcState.pc, &code_buffer, b);
blocks.FinalizeBlock(block_num, jo.enableBlocklink, BlockPtr); blocks.FinalizeBlock(block_num, jo.enableBlocklink, BlockPtr);
} }
void JitArm::Break(UGeckoInstruction inst) void JitArm::Break(UGeckoInstruction inst)
@ -355,13 +359,13 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
// Downcount flag check, Only valid for linked blocks // Downcount flag check, Only valid for linked blocks
{ {
FixupBranch skip = B_CC(CC_PL); SetCC(CC_MI);
ARMReg rA = gpr.GetReg(false); ARMReg rA = gpr.GetReg(false);
MOVI2R(rA, js.blockStart); MOVI2R(rA, js.blockStart);
STR(rA, R9, PPCSTATE_OFF(pc)); STR(rA, R9, PPCSTATE_OFF(pc));
MOVI2R(rA, (u32)asm_routines.doTiming); MOVI2R(rA, (u32)asm_routines.doTiming);
B(rA); B(rA);
SetJumpTarget(skip); SetCC();
} }
const u8 *normalEntry = GetCodePtr(); const u8 *normalEntry = GetCodePtr();
@ -379,11 +383,11 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
MOVI2R(C, js.blockStart); // R3 MOVI2R(C, js.blockStart); // R3
LDR(A, R9, PPCSTATE_OFF(msr)); LDR(A, R9, PPCSTATE_OFF(msr));
TST(A, Shift); TST(A, Shift);
FixupBranch b1 = B_CC(CC_NEQ); SetCC(CC_EQ);
STR(C, R9, PPCSTATE_OFF(pc)); STR(C, R9, PPCSTATE_OFF(pc));
MOVI2R(A, (u32)asm_routines.fpException); MOVI2R(A, (u32)asm_routines.fpException);
B(A); B(A);
SetJumpTarget(b1); SetCC();
gpr.Unlock(A, C); gpr.Unlock(A, C);
} }
// Conditionally add profiling code. // Conditionally add profiling code.
@ -446,8 +450,9 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
if (jo.optimizeGatherPipe && js.fifoBytesThisBlock >= 32) if (jo.optimizeGatherPipe && js.fifoBytesThisBlock >= 32)
{ {
js.fifoBytesThisBlock -= 32; js.fifoBytesThisBlock -= 32;
// TODO: This needs thunkmanager for ARM PUSH(4, R0, R1, R2, R3);
//ARMABI_CallFunction(thunks.ProtectFunction((void *)&GPFifo::CheckGatherPipe, 0)); QuickCallFunction(R14, (void*)&GPFifo::CheckGatherPipe);
POP(4, R0, R1, R2, R3);
} }
if (Core::g_CoreStartupParameter.bEnableDebugging) if (Core::g_CoreStartupParameter.bEnableDebugging)
{ {

29
Source/Core/Core/Src/PowerPC/JitArm32/JitAsm.cpp
View File

@ -65,34 +65,30 @@ void JitArmAsmRoutineManager::Generate()
// It runs though to the compiling portion if it isn't found // It runs though to the compiling portion if it isn't found
LDR(R12, R9, PPCSTATE_OFF(pc));// Load the current PC into R12 LDR(R12, R9, PPCSTATE_OFF(pc));// Load the current PC into R12
MOVI2R(R14, JIT_ICACHE_MASK); // Potential for optimization Operand2 iCacheMask = Operand2(0xE, 2); // JIT_ICACHE_MASK
AND(R12, R12, R14); // R12 contains PC & JIT_ICACHE_MASK here. BIC(R12, R12, iCacheMask); // R12 contains PC & JIT_ICACHE_MASK here.
// Confirmed good to this point 08-03-12
MOVI2R(R14, (u32)jit->GetBlockCache()->GetICache()); MOVI2R(R14, (u32)jit->GetBlockCache()->GetICache());
// Confirmed That this loads the base iCache Location correctly 08-04-12
LDR(R12, R14, R12); // R12 contains iCache[PC & JIT_ICACHE_MASK] here LDR(R12, R14, R12); // R12 contains iCache[PC & JIT_ICACHE_MASK] here
// R12 Confirmed this is the correct iCache Location loaded. // R12 Confirmed this is the correct iCache Location loaded.
TST(R12, 0xFC); // Test to see if it is a JIT block. TST(R12, 0xFC); // Test to see if it is a JIT block.
SetCC(CC_EQ); // Only run next part if R12 is zero SetCC(CC_EQ);
// Success, it is our Jitblock. // Success, it is our Jitblock.
MOVI2R(R14, (u32)jit->GetBlockCache()->GetCodePointers()); MOVI2R(R14, (u32)jit->GetBlockCache()->GetCodePointers());
// LDR R14 right here to get CodePointers()[0] pointer. // LDR R14 right here to get CodePointers()[0] pointer.
REV(R12, R12); // Reversing this gives us our JITblock. REV(R12, R12); // Reversing this gives us our JITblock.
LSL(R12, R12, 2); // Multiply by four because address locations are u32 in size LSL(R12, R12, 2); // Multiply by four because address locations are u32 in size
LDR(R14, R14, R12); // Load the block address in to R14 LDR(R14, R14, R12); // Load the block address in to R14
B(R14); B(R14);
// No need to jump anywhere after here, the block will go back to dispatcher start
FixupBranch NextBlock = B(); // Jump to end so we can start a new block SetCC();
SetCC(); // Return to always executing codes
// If we get to this point, that means that we don't have the block cached to execute // If we get to this point, that means that we don't have the block cached to execute
// So call ArmJit to compile the block and then execute it. // So call ArmJit to compile the block and then execute it.
MOVI2R(R14, (u32)&Jit); MOVI2R(R14, (u32)&Jit);
LDR(R0, R9, PPCSTATE_OFF(pc));
BL(R14); BL(R14);
B(dispatcherNoCheck); B(dispatcherNoCheck);
@ -129,7 +125,6 @@ void JitArmAsmRoutineManager::Generate()
TST(R0, R1); TST(R0, R1);
FixupBranch Exit = B_CC(CC_NEQ); FixupBranch Exit = B_CC(CC_NEQ);
SetJumpTarget(NextBlock);
B(dispatcher); B(dispatcher);
SetJumpTarget(Exit); SetJumpTarget(Exit);