JitIL: a couple small optimizations.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2286 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -326,6 +326,19 @@ InstLoc IRBuilder::FoldUOp(unsigned Opcode, InstLoc Op1, unsigned extra) {
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if (Opcode == DoubleToSingle) {
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if (getOpcode(*Op1) == DupSingleToMReg)
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return getOp1(Op1);
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if (getOpcode(*Op1) >= FDMul || getOpcode(*Op1) <= FDSub) {
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InstLoc OOp1 = getOp1(Op1), OOp2 = getOp2(Op1);
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if (getOpcode(*OOp1) == DupSingleToMReg &&
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getOpcode(*OOp2) == DupSingleToMReg) {
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if (getOpcode(*Op1) == FDMul) {
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return FoldBiOp(FSMul, getOp1(OOp1), getOp2(OOp2));
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} else if (getOpcode(*Op1) == FDAdd) {
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return FoldBiOp(FSAdd, getOp1(OOp1), getOp2(OOp2));
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} else if (getOpcode(*Op1) == FDSub) {
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return FoldBiOp(FSSub, getOp1(OOp1), getOp2(OOp2));
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}
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}
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}
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}
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return EmitUOp(Opcode, Op1, extra);
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@ -1341,6 +1354,7 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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case StoreCTR:
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case StoreMSR:
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case StoreGQR:
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case StoreSRR:
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case StoreFReg:
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if (!isImm(*getOp1(I)))
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regMarkUse(RI, I, getOp1(I), 1);
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@ -1527,6 +1541,13 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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regNormalRegClear(RI, I);
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break;
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}
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case StoreSRR: {
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unsigned srr = *I >> 16;
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regStoreInstToConstLoc(RI, 32, getOp1(I),
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&PowerPC::ppcState.spr[SPR_SRR0+srr]);
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regNormalRegClear(RI, I);
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break;
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}
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case StoreCarry: {
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Jit->CMP(32, regLocForInst(RI, getOp1(I)), Imm8(0));
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FixupBranch nocarry = Jit->J_CC(CC_Z);
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@ -56,6 +56,7 @@ namespace IREmitter {
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StoreMSR,
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StoreFPRF,
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StoreGQR,
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StoreSRR,
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// Arbitrary interpreter instruction
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InterpreterFallback,
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@ -491,6 +492,9 @@ namespace IREmitter {
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InstLoc EmitStoreGQR(InstLoc op1, unsigned gqr) {
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return FoldUOp(StoreGQR, op1, gqr);
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}
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InstLoc EmitStoreSRR(InstLoc op1, unsigned srr) {
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return FoldUOp(StoreSRR, op1, srr);
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}
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void StartBackPass() { curReadPtr = &InstList[InstList.size()]; }
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void StartForwardPass() { curReadPtr = &InstList[0]; }
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@ -55,6 +55,10 @@
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case SPR_GQR0 + 7:
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ibuild.EmitStoreGQR(ibuild.EmitLoadGReg(inst.RD), iIndex - SPR_GQR0);
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return;
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case SPR_SRR0:
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case SPR_SRR1:
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ibuild.EmitStoreSRR(ibuild.EmitLoadGReg(inst.RD), iIndex - SPR_SRR0);
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return;
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default:
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Default(inst);
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return;
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