From 9e970bcb30d1281c1e48b5ebec5f734ad7c1a022 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sat, 19 Aug 2023 13:51:03 +0200 Subject: [PATCH] JitArm64: Optiming shifting and masking PC in slow dispatcher Instead of shifting left by 1, we can first shift right by 2 and then left by 3. This is both faster and smaller, because we get the right shift for free with the masking and the left shift for free with the address calculation. It also happens to match the pseudocode more closely, which is always nice for readability. --- Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp index 0cfece976c..5cd554ce89 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp @@ -123,11 +123,10 @@ void JitArm64::GenerateAsm() ARM64Reg msr2 = ARM64Reg::W13; // iCache[(address >> 2) & iCache_Mask]; - ORR(pc_masked, ARM64Reg::WZR, - LogicalImm(JitBaseBlockCache::FAST_BLOCK_MAP_FALLBACK_MASK << 3, 32)); - AND(pc_masked, pc_masked, DISPATCHER_PC, ArithOption(DISPATCHER_PC, ShiftType::LSL, 1)); + UBFX(pc_masked, DISPATCHER_PC, 2, + MathUtil::IntLog2(JitBaseBlockCache::FAST_BLOCK_MAP_FALLBACK_ELEMENTS) - 2); MOVP2R(cache_base, GetBlockCache()->GetFastBlockMapFallback()); - LDR(block, cache_base, EncodeRegTo64(pc_masked)); + LDR(block, cache_base, ArithOption(EncodeRegTo64(pc_masked), true)); FixupBranch not_found = CBZ(block); // b.effectiveAddress != addr || b.msrBits != msr