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JitCache: Move JitBlock config variable.

This commit is contained in:
degasus 2017-01-15 13:23:46 +01:00
parent 352909fc4c
commit 9d58127dec
4 changed files with 10 additions and 14 deletions
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2
Source/Core/Core/PowerPC/Jit64/JitAsm.cpp
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@ -126,7 +126,7 @@ void Jit64AsmRoutineManager::Generate()
// Check both block.effectiveAddress and block.msrBits. // Check both block.effectiveAddress and block.msrBits.
MOV(32, R(RSCRATCH2), PPCSTATE(msr)); MOV(32, R(RSCRATCH2), PPCSTATE(msr));
AND(32, R(RSCRATCH2), Imm32(JitBlock::JIT_CACHE_MSR_MASK)); AND(32, R(RSCRATCH2), Imm32(JitBaseBlockCache::JIT_CACHE_MSR_MASK));
SHL(64, R(RSCRATCH2), Imm8(32)); SHL(64, R(RSCRATCH2), Imm8(32));
MOV(32, R(RSCRATCH_EXTRA), PPCSTATE(pc)); MOV(32, R(RSCRATCH_EXTRA), PPCSTATE(pc));
OR(64, R(RSCRATCH2), R(RSCRATCH_EXTRA)); OR(64, R(RSCRATCH2), R(RSCRATCH_EXTRA));

2
Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
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@ -88,7 +88,7 @@ void JitArm64::GenerateAsm()
FixupBranch pc_missmatch = B(CC_NEQ); FixupBranch pc_missmatch = B(CC_NEQ);
LDR(INDEX_UNSIGNED, pc_and_msr2, PPC_REG, PPCSTATE_OFF(msr)); LDR(INDEX_UNSIGNED, pc_and_msr2, PPC_REG, PPCSTATE_OFF(msr));
ANDI2R(pc_and_msr2, pc_and_msr2, JitBlock::JIT_CACHE_MSR_MASK); ANDI2R(pc_and_msr2, pc_and_msr2, JitBaseBlockCache::JIT_CACHE_MSR_MASK);
LDR(INDEX_UNSIGNED, pc_and_msr, block, offsetof(JitBlock, msrBits)); LDR(INDEX_UNSIGNED, pc_and_msr, block, offsetof(JitBlock, msrBits));
CMP(pc_and_msr, pc_and_msr2); CMP(pc_and_msr, pc_and_msr2);
FixupBranch msr_missmatch = B(CC_NEQ); FixupBranch msr_missmatch = B(CC_NEQ);

9
Source/Core/Core/PowerPC/JitCommon/JitCache.cpp
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@ -116,7 +116,7 @@ JitBlock* JitBaseBlockCache::AllocateBlock(u32 em_address)
b.invalid = false; b.invalid = false;
b.effectiveAddress = em_address; b.effectiveAddress = em_address;
b.physicalAddress = PowerPC::JitCache_TranslateAddress(em_address).address; b.physicalAddress = PowerPC::JitCache_TranslateAddress(em_address).address;
b.msrBits = MSR & JitBlock::JIT_CACHE_MSR_MASK; b.msrBits = MSR & JIT_CACHE_MSR_MASK;
b.linkData.clear(); b.linkData.clear();
b.in_icache = 0; b.in_icache = 0;
num_blocks++; // commit the current block num_blocks++; // commit the current block
@ -180,7 +180,7 @@ JitBlock* JitBaseBlockCache::GetBlockFromStartAddress(u32 addr, u32 msr)
JitBlock* b = map_result->second; JitBlock* b = map_result->second;
if (b->invalid || b->effectiveAddress != addr || if (b->invalid || b->effectiveAddress != addr ||
b->msrBits != (msr & JitBlock::JIT_CACHE_MSR_MASK)) b->msrBits != (msr & JIT_CACHE_MSR_MASK))
return nullptr; return nullptr;
return b; return b;
} }
@ -189,10 +189,9 @@ const u8* JitBaseBlockCache::Dispatch()
{ {
JitBlock* block = iCache[FastLookupEntryForAddress(PC)]; JitBlock* block = iCache[FastLookupEntryForAddress(PC)];
while (!block || block->effectiveAddress != PC || while (!block || block->effectiveAddress != PC || block->msrBits != (MSR & JIT_CACHE_MSR_MASK))
block->msrBits != (MSR & JitBlock::JIT_CACHE_MSR_MASK))
{ {
MoveBlockIntoFastCache(PC, MSR & JitBlock::JIT_CACHE_MSR_MASK); MoveBlockIntoFastCache(PC, MSR & JIT_CACHE_MSR_MASK);
block = iCache[FastLookupEntryForAddress(PC)]; block = iCache[FastLookupEntryForAddress(PC)];
} }

11
Source/Core/Core/PowerPC/JitCommon/JitCache.h
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@ -24,13 +24,6 @@ class JitBase;
// address. // address.
struct JitBlock struct JitBlock
{ {
enum
{
// Mask for the MSR bits which determine whether a compiled block
// is valid (MSR.IR and MSR.DR, the address translation bits).
JIT_CACHE_MSR_MASK = 0x30,
};
// A special entry point for block linking; usually used to check the // A special entry point for block linking; usually used to check the
// downcount. // downcount.
const u8* checkedEntry; const u8* checkedEntry;
@ -115,6 +108,10 @@ public:
class JitBaseBlockCache class JitBaseBlockCache
{ {
public: public:
// Mask for the MSR bits which determine whether a compiled block
// is valid (MSR.IR and MSR.DR, the address translation bits).
static constexpr u32 JIT_CACHE_MSR_MASK = 0x30;
static constexpr int MAX_NUM_BLOCKS = 65536 * 2; static constexpr int MAX_NUM_BLOCKS = 65536 * 2;
static constexpr u32 iCache_Num_Elements = 0x10000; static constexpr u32 iCache_Num_Elements = 0x10000;
static constexpr u32 iCache_Mask = iCache_Num_Elements - 1; static constexpr u32 iCache_Mask = iCache_Num_Elements - 1;