diff --git a/Source/Core/DSPCore/Src/DSPEmitter.h b/Source/Core/DSPCore/Src/DSPEmitter.h
index e84442bc5e..bbbfb5b196 100644
--- a/Source/Core/DSPCore/Src/DSPEmitter.h
+++ b/Source/Core/DSPCore/Src/DSPEmitter.h
@@ -150,12 +150,15 @@ public:
 	void lrr(const UDSPInstruction opc);
 	void lrrd(const UDSPInstruction opc);
 	void lrri(const UDSPInstruction opc);
+	void lrrn(const UDSPInstruction opc);
 	void srr(const UDSPInstruction opc);
 	void srrd(const UDSPInstruction opc);
 	void srri(const UDSPInstruction opc);
+	void srrn(const UDSPInstruction opc);
 	void ilrr(const UDSPInstruction opc);
 	void ilrrd(const UDSPInstruction opc);
 	void ilrri(const UDSPInstruction opc);
+	void ilrrn(const UDSPInstruction opc);
 
 	// Arithmetic
 	void clr(const UDSPInstruction opc);
diff --git a/Source/Core/DSPCore/Src/DSPTables.cpp b/Source/Core/DSPCore/Src/DSPTables.cpp
index 8f704a530c..80da03c190 100644
--- a/Source/Core/DSPCore/Src/DSPTables.cpp
+++ b/Source/Core/DSPCore/Src/DSPTables.cpp
@@ -181,7 +181,7 @@ const DSPOPCTemplate opcodes[] =
 	{"ILRR",	0x0210, 0xfefc, DSPInterpreter::ilrr,    &DSPEmitter::ilrr,   1, 2, {{P_ACCM, 1, 0, 8, 0x0100},    {P_PRG, 1, 0, 0, 0x0003}},                               false, false, false, false, false},
 	{"ILRRD",	0x0214, 0xfefc, DSPInterpreter::ilrrd,   &DSPEmitter::ilrrd,  1, 2, {{P_ACCM, 1, 0, 8, 0x0100},    {P_PRG, 1, 0, 0, 0x0003}},                               false, false, false, false, false},
 	{"ILRRI",	0x0218, 0xfefc, DSPInterpreter::ilrri,   &DSPEmitter::ilrri,  1, 2, {{P_ACCM, 1, 0, 8, 0x0100},    {P_PRG, 1, 0, 0, 0x0003}},                               false, false, false, false, false},
-	{"ILRRN",	0x021c, 0xfefc, DSPInterpreter::ilrrn,   NULL,                1, 2, {{P_ACCM, 1, 0, 8, 0x0100},    {P_PRG, 1, 0, 0, 0x0003}},                               false, false, false, false, false},
+	{"ILRRN",	0x021c, 0xfefc, DSPInterpreter::ilrrn,   &DSPEmitter::ilrrn,  1, 2, {{P_ACCM, 1, 0, 8, 0x0100},    {P_PRG, 1, 0, 0, 0x0003}},                               false, false, false, false, false},
 
 	// LOOPS
 	{"LOOP",	0x0040, 0xffe0, DSPInterpreter::loop,    &DSPEmitter::loop,   1, 1, {{P_REG, 1, 0, 0, 0x001f}},                                                             false, true, false, true, false},
@@ -193,12 +193,12 @@ const DSPOPCTemplate opcodes[] =
 	{"LRR",		0x1800, 0xff80, DSPInterpreter::lrr,     &DSPEmitter::lrr,    1, 2, {{P_REG, 1, 0, 0, 0x001f},     {P_PRG, 1, 0, 5, 0x0060}},                               false, false, false, false, false},
 	{"LRRD",	0x1880, 0xff80, DSPInterpreter::lrrd,    &DSPEmitter::lrrd,   1, 2, {{P_REG, 1, 0, 0, 0x001f},     {P_PRG, 1, 0, 5, 0x0060}},                               false, false, false, false, false},
 	{"LRRI",	0x1900, 0xff80, DSPInterpreter::lrri,    &DSPEmitter::lrri,   1, 2, {{P_REG, 1, 0, 0, 0x001f},     {P_PRG, 1, 0, 5, 0x0060}},                               false, false, false, false, false},
-	{"LRRN",	0x1980, 0xff80, DSPInterpreter::lrrn,    NULL,                1, 2, {{P_REG, 1, 0, 0, 0x001f},     {P_PRG, 1, 0, 5, 0x0060}},                               false, false, false, false, false},
+	{"LRRN",	0x1980, 0xff80, DSPInterpreter::lrrn,    &DSPEmitter::lrrn,   1, 2, {{P_REG, 1, 0, 0, 0x001f},     {P_PRG, 1, 0, 5, 0x0060}},                               false, false, false, false, false},
 
 	{"SRR",		0x1a00, 0xff80, DSPInterpreter::srr,     &DSPEmitter::srr,    1, 2, {{P_PRG, 1, 0, 5, 0x0060},     {P_REG, 1, 0, 0, 0x001f}},                               false, false, false, false, false},
 	{"SRRD",	0x1a80, 0xff80, DSPInterpreter::srrd,    &DSPEmitter::srrd,   1, 2, {{P_PRG, 1, 0, 5, 0x0060},     {P_REG, 1, 0, 0, 0x001f}},                               false, false, false, false, false},
 	{"SRRI",	0x1b00, 0xff80, DSPInterpreter::srri,    &DSPEmitter::srri,   1, 2, {{P_PRG, 1, 0, 5, 0x0060},     {P_REG, 1, 0, 0, 0x001f}},                               false, false, false, false, false},
-	{"SRRN",	0x1b80, 0xff80, DSPInterpreter::srrn,    NULL,                1, 2, {{P_PRG, 1, 0, 5, 0x0060},     {P_REG, 1, 0, 0, 0x001f}},                               false, false, false, false, false},
+	{"SRRN",	0x1b80, 0xff80, DSPInterpreter::srrn,    &DSPEmitter::srrn,   1, 2, {{P_PRG, 1, 0, 5, 0x0060},     {P_REG, 1, 0, 0, 0x001f}},                               false, false, false, false, false},
 
 	//2
 	{"LRS",		0x2000, 0xf800, DSPInterpreter::lrs,     &DSPEmitter::lrs,    1, 2, {{P_REG18, 1, 0, 8, 0x0700},   {P_MEM, 1, 0, 0, 0x00ff}},                               false, false, false, false, false},
diff --git a/Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp b/Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp
index 0b04be9eb2..13efb31b56 100644
--- a/Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp
+++ b/Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp
@@ -124,11 +124,6 @@ void DSPEmitter::lrr(const UDSPInstruction opc)
 	u8 dreg = opc & 0x1f;
 
 	dsp_op_read_reg(sreg, ECX);
-#ifdef _M_IX86 // All32
-	MOVZX(32, 16, ECX, R(ECX));
-#else
-	MOVZX(64, 16, ECX, R(ECX));
-#endif
 	dmem_read();
 	dsp_op_write_reg(dreg, EAX);
 	dsp_conditional_extend_accum(dreg);
@@ -145,11 +140,6 @@ void DSPEmitter::lrrd(const UDSPInstruction opc)
 	u8 dreg = opc & 0x1f;
 
 	dsp_op_read_reg(sreg, ECX);
-#ifdef _M_IX86 // All32
-	MOVZX(32, 16, ECX, R(ECX));
-#else
-	MOVZX(64, 16, ECX, R(ECX));
-#endif
 	dmem_read();
 	dsp_op_write_reg(dreg, EAX);
 	dsp_conditional_extend_accum(dreg);
@@ -167,11 +157,6 @@ void DSPEmitter::lrri(const UDSPInstruction opc)
 	u8 dreg = opc & 0x1f;
 
 	dsp_op_read_reg(sreg, ECX);
-#ifdef _M_IX86 // All32
-	MOVZX(32, 16, ECX, R(ECX));
-#else
-	MOVZX(64, 16, ECX, R(ECX));
-#endif
 	dmem_read();
 	dsp_op_write_reg(dreg, EAX);
 	dsp_conditional_extend_accum(dreg);
@@ -183,16 +168,17 @@ void DSPEmitter::lrri(const UDSPInstruction opc)
 // Move value from data memory pointed by addressing register $S to register $D.
 // Add indexing register $(0x4+S) to register $S. 
 // FIXME: Perform additional operation depending on destination register.
-//void DSPEmitter::lrrn(const UDSPInstruction opc)
-//{
-//	u8 sreg = (opc >> 5) & 0x3;
-//	u8 dreg = opc & 0x1f;
+void DSPEmitter::lrrn(const UDSPInstruction opc)
+{
+	u8 sreg = (opc >> 5) & 0x3;
+	u8 dreg = opc & 0x1f;
 
-//	u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
-//	dsp_op_write_reg(dreg, val);
-//	dsp_conditional_extend_accum(dreg);
-//	g_dsp.r[sreg] = dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
-//}
+	dsp_op_read_reg(sreg, ECX);
+	dmem_read();
+	dsp_op_write_reg(dreg, EAX);
+	dsp_conditional_extend_accum(dreg);
+	increase_addr_reg(sreg);
+}
 
 // SRR @$D, $S
 // 0001 1010 0dds ssss
@@ -261,15 +247,21 @@ void DSPEmitter::srri(const UDSPInstruction opc)
 // Store value from source register $S to a memory location pointed by
 // addressing register $D. Add DSP_REG_IX0 register to register $D.
 // FIXME: Perform additional operation depending on source register.
-//void DSPEmitter::srrn(const UDSPInstruction opc)
-//{
-//	u8 dreg = (opc >> 5) & 0x3;
-//	u8 sreg = opc & 0x1f;
+void DSPEmitter::srrn(const UDSPInstruction opc)
+{
+	u8 dreg = (opc >> 5) & 0x3;
+	u8 sreg = opc & 0x1f;
 
-//	u16 val = dsp_op_read_reg(sreg);
-//	dsp_dmem_write(g_dsp.r[dreg], val);
-//	g_dsp.r[dreg] = dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
-//}
+	dsp_op_read_reg(sreg, ECX);
+#ifdef _M_IX86 // All32
+	MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
+#else
+	MOV(64, R(R11), ImmPtr(&g_dsp.r));
+	MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
+#endif
+	dmem_write();
+	increase_addr_reg(dreg);
+}
 
 // ILRR $acD.m, @$arS
 // 0000 001d 0001 00ss
@@ -353,15 +345,25 @@ void DSPEmitter::ilrri(const UDSPInstruction opc)
 // Move value from instruction memory pointed by addressing register
 // $arS to mid accumulator register $acD.m. Add corresponding indexing
 // register $ixS to addressing register $arS.
-//void DSPEmitter::ilrrn(const UDSPInstruction opc)
-//{
-//	u16 reg  = opc & 0x3;
-//	u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
+void DSPEmitter::ilrrn(const UDSPInstruction opc)
+{
+	u16 reg  = opc & 0x3;
+	u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
 
-//	g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
-//	dsp_conditional_extend_accum(dreg);
-//	g_dsp.r[reg] = dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]);
-//}
+#ifdef _M_IX86 // All32
+	MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
+#else
+	MOV(64, R(R11), ImmPtr(&g_dsp.r));
+	MOVZX(64, 16, RCX, MDisp(R11,reg*2));
+#endif
+	imem_read();
+#ifdef _M_IX86 // All32
+	MOV(16, M(&g_dsp.r[dreg]), R(EAX));
+#else
+	MOV(64, R(R11), ImmPtr(&g_dsp.r));
+	MOV(16, MDisp(R11,dreg*2), R(RAX));
+#endif
+	dsp_conditional_extend_accum(dreg);
+	increase_addr_reg(reg);
+}
 
-//}  // namespace
-//
diff --git a/Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp b/Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp
index 6a30f5f922..7de5d5a668 100644
--- a/Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp
+++ b/Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp
@@ -420,10 +420,12 @@ void DSPEmitter::dmem_read()
 	CMP(16, R(ECX), Imm16(0x0fff));
 	FixupBranch dram = J_CC(CC_A);
 	//	return g_dsp.dram[addr & DSP_DRAM_MASK];
-	AND(16, R(ECX), Imm16(DSP_DRAM_MASK));
 #ifdef _M_X64
+	AND(16, R(ECX), Imm16(DSP_DRAM_MASK));
+	MOVZX(64, 16, RCX, R(RCX));
 	MOV(64, R(ESI), ImmPtr(g_dsp.dram));
 #else
+	AND(32, R(ECX), Imm32(DSP_DRAM_MASK));
 	MOV(32, R(ESI), ImmPtr(g_dsp.dram));
 #endif
 	MOV(16, R(EAX), MComplex(ESI, ECX, 2, 0));
@@ -434,10 +436,12 @@ void DSPEmitter::dmem_read()
 	CMP(16, R(ECX), Imm16(0x1fff));
 	FixupBranch ifx = J_CC(CC_A);
 	//		return g_dsp.coef[addr & DSP_COEF_MASK];
-	AND(16, R(ECX), Imm16(DSP_COEF_MASK));
 #ifdef _M_X64
+	AND(16, R(ECX), Imm16(DSP_COEF_MASK));
+	MOVZX(64, 16, RCX, R(RCX));
 	MOV(64, R(ESI), ImmPtr(g_dsp.coef));
 #else
+	AND(32, R(ECX), Imm32(DSP_COEF_MASK));
 	MOV(32, R(ESI), ImmPtr(g_dsp.coef));
 #endif
 	MOV(16, R(EAX), MComplex(ESI,ECX,2,0));