Implemented MMU:
* Added BAT algorithm * Page Address translation algorithm is now used in all games * Added TLB cache * Temporarily forced JITIL to use the slow memory access for Win32 when playing tlbhack games. F-ZERO GX is now playable. It works only on JITIL in the 32bit version. It works in both JIT and JITIL on x64. The MMU code may fix other games that are crashing. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4839 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
skidau
parent
61eed07ec4
commit
9c264a1047
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@ -161,7 +161,8 @@ enum XCheckTLBFlag
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FLAG_WRITE,
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FLAG_OPCODE,
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};
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u32 CheckDTLB(u32 _Address, XCheckTLBFlag _Flag);
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u32 TranslatePageAddress(u32 _Address, XCheckTLBFlag _Flag);
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u32 TranslateBlockAddress(u32 _Address);
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extern u32 pagetable_base;
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extern u32 pagetable_hashmask;
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@ -178,23 +178,27 @@ void ReadFromHardware(T &_var, u32 em_address, u32 effective_address, Memory::XC
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{
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PanicAlert("READ: Invalid address: %08x", em_address);
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}
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/* If we get this far we may be in the TLB area */
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else if (bFakeVMEM && ((em_address &0xF0000000) == 0x70000000))
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{
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// fake VMEM
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_var = bswap((*(const T*)&m_pFakeVMEM[em_address & FAKEVMEM_MASK]));
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}
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else
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{
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/*if (bFakeVMEM && ((em_address & 0xFE000000) == 0x7e000000) )*/
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/*F-Zero:*/if (bFakeVMEM)
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// MMU
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u32 tlb_addr = TranslateBlockAddress(em_address);
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if (tlb_addr == 0)
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{
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_var = bswap((*(const T*)&m_pFakeVMEM[em_address & FAKEVMEM_MASK]));
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}
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else {/* LOG(MEMMAP,"READ (unknown): %08x (PC: %08x)",em_address,PC);*/
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/*PanicAlert("READ: Unknown Address", "1", MB_OK);*/
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u32 TmpAddress = CheckDTLB(effective_address, flag);
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TmpAddress = (TmpAddress & 0xFFFFFFF0) | (em_address & 0xF);
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if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
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_var = bswap((*(const T*)&m_pRAM[TmpAddress & RAM_MASK]));
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tlb_addr = TranslatePageAddress(em_address, flag);
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if (tlb_addr != 0)
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_var = bswap((*(const T*)&m_pRAM[tlb_addr & RAM_MASK]));
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else
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PanicAlert("READ: Invalid address: %08x", em_address);
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}
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else
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_var = bswap((*(const T*)&m_pRAM[tlb_addr & RAM_MASK]));
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}
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/* Debugging: CheckForBadAddresses##_type(em_address, _var, true);*/
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}
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@ -263,19 +267,26 @@ void WriteToHardware(u32 em_address, const T data, u32 effective_address, Memory
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ERROR_LOG(MEMMAP,"WRITE: Cache address out of bounds (addr: %08x data: %08x)", em_address, data);
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/* PanicAlert("WRITE: Cache address %08x out of bounds", em_address); */
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}
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else if (bFakeVMEM && ((em_address &0xF0000000) == 0x70000000))
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{
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// fake VMEM
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*(T*)&m_pFakeVMEM[em_address & FAKEVMEM_MASK] = bswap(data);
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}
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else
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{
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/*if (bFakeVMEM && ((em_address & 0xFE000000) == 0x7e000000))*/
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/*F-Zero: */ if (bFakeVMEM)
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// MMU
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u32 tlb_addr = TranslateBlockAddress(em_address);
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if (tlb_addr == 0)
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{
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*(T*)&m_pFakeVMEM[em_address & FAKEVMEM_MASK] = bswap(data);
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return;
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tlb_addr = TranslatePageAddress(em_address, flag);
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if (tlb_addr != 0)
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*(T*)&m_pRAM[tlb_addr & RAM_MASK] = bswap(data);
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else
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PanicAlert("WRITE: Invalid address: %08x", em_address);
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}
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/* LOG(MEMMAP,"WRITE: %08x (PC: %08x)",em_address,PC);*/
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/*MessageBox(NULL, "WRITE: unknown Address", "1", MB_OK);*/
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u32 tmpAddress = CheckDTLB(effective_address, flag);
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tmpAddress = (tmpAddress & 0xFFFFFFF0) | (em_address & 0xF);
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*(T*)&m_pRAM[tmpAddress & RAM_MASK] = bswap(data);
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else
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*(T*)&m_pRAM[tlb_addr & RAM_MASK] = bswap(data);
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}
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}
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// =====================
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@ -460,12 +471,6 @@ void WriteUnchecked_U32(const u32 _iValue, const u32 _Address)
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{
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WriteToHardware<u32>(_Address, _iValue, _Address, FLAG_NO_EXCEPTION);
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}
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// =====================
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// *********************************************************************************
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// Warning: Test Area
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@ -625,29 +630,16 @@ void SDRUpdated()
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pagetable_hashmask = ((xx<<10)|0x3ff);
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}
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u32 CheckDTLB(u32 _Address, XCheckTLBFlag _Flag)
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// Page Address Translation
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u32 TranslatePageAddress(u32 _Address, XCheckTLBFlag _Flag)
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{
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// Don't show the warnings if we are testing this code
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if(!bFakeVMEM)
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{
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if (Core::GetStartupParameter().bWii) {
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// TLB is never used on Wii (except linux and stuff, but we don't care about that)
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PanicAlert("%s invalid memory region (0x%08x)\n\n"
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"There is no way to recover from this error,"
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"so Dolphin will now exit. Sorry!",
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_Flag == FLAG_WRITE ? "Write to" : "Read from", _Address);
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// TLB cache
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for (int i = 0; i < 16; i++) {
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if ((_Address & ~0xfff) == (PowerPC::ppcState.tlb_va[(PowerPC::ppcState.tlb_last + i) & 15])) {
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u32 result = PowerPC::ppcState.tlb_pa[(PowerPC::ppcState.tlb_last + i) & 15] | (_Address & 0xfff);
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PowerPC::ppcState.tlb_last = i;
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return result;
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}
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else {
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PanicAlert("%s invalid memory region (0x%08x)\n\n"
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"This is either the game crashing randomly, or a TLB write."
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"Several games uses the TLB to map memory. This\n"
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"function is not supported in Dolphin. "
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"Unfortunately there is no way to recover from this error,"
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"so Dolphin will now exit abruptly. Sorry!",
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_Flag == FLAG_WRITE ? "Write to" : "Read from", _Address);
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}
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exit(0);
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}
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u32 sr = PowerPC::ppcState.sr[EA_SR(_Address)];
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@ -661,7 +653,7 @@ u32 CheckDTLB(u32 _Address, XCheckTLBFlag _Flag)
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// hash function no 1 "xor" .360
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u32 hash1 = (VSID ^ page_index);
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u32 pteg_addr = ((hash1 & pagetable_hashmask)<<6) | pagetable_base;
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u32 pteg_addr = ((hash1 & pagetable_hashmask)<<6) | pagetable_base;
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// hash1
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for (int i = 0; i < 8; i++)
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@ -676,6 +668,12 @@ u32 CheckDTLB(u32 _Address, XCheckTLBFlag _Flag)
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UPTE2 PTE2;
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PTE2.Hex = bswap((*(u32*)&pRAM[(pteg_addr + 4)]));
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// TLB cache
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PowerPC::ppcState.tlb_last++;
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PowerPC::ppcState.tlb_last &= 15;
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PowerPC::ppcState.tlb_pa[PowerPC::ppcState.tlb_last] = PTE2.RPN << 12;
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PowerPC::ppcState.tlb_va[PowerPC::ppcState.tlb_last] = _Address & ~0xfff;
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// set the access bits
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switch (_Flag)
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{
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@ -702,15 +700,25 @@ u32 CheckDTLB(u32 _Address, XCheckTLBFlag _Flag)
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{
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if (VSID == PTE1_VSID(pte) && (api == PTE1_API(pte)))
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{
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PanicAlert("TLB: Address found at the second hash function.\n"
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"i have never seen this before");
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UPTE2 PTE2;
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PTE2.Hex = bswap((*(u32*)&pRAM[(pteg_addr + 4)]));
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pte = bswap(*(u32*)&pRAM[(pteg_addr+4)]);
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// TLB cache
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PowerPC::ppcState.tlb_last++;
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PowerPC::ppcState.tlb_last &= 15;
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PowerPC::ppcState.tlb_pa[PowerPC::ppcState.tlb_last] = PTE2.RPN;
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PowerPC::ppcState.tlb_va[PowerPC::ppcState.tlb_last] = _Address & ~0xfff;
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u32 physAddress = PTE2_RPN(pte) | offset;
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switch (_Flag)
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{
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case FLAG_READ: PTE2.R = 1; break;
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case FLAG_WRITE: PTE2.C = 1; break;
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case FLAG_NO_EXCEPTION: break;
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case FLAG_OPCODE: break;
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}
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*(u32*)&pRAM[(pteg_addr + 4)] = bswap(PTE2.Hex);
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// missing access bits
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return physAddress;
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return ((PTE2.RPN << 12) | offset);
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}
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}
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pteg_addr+=8;
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@ -738,7 +746,63 @@ u32 CheckDTLB(u32 _Address, XCheckTLBFlag _Flag)
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return 0;
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}
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// ***********************
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#define BATU_BEPI(v) ((v)&0xfffe0000)
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#define BATU_BL(v) (((v)&0x1ffc)>>2)
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#define BATU_Vs (1<<1)
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#define BATU_Vp (1)
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#define BATL_BRPN(v) ((v)&0xfffe0000)
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#define BAT_EA_OFFSET(v) ((v)&0x1ffff)
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#define BAT_EA_11(v) ((v)&0x0ffe0000)
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#define BAT_EA_4(v) ((v)&0xf0000000)
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// Block Address Translation
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u32 TranslateBlockAddress(u32 addr)
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{
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u32 result = 0;
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UReg_MSR& m_MSR = ((UReg_MSR&)PowerPC::ppcState.msr);
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for (int i=0; i<4; i++) {
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u32 bl17 = ~(BATU_BL(PowerPC::ppcState.spr[SPR_DBAT0U + i * 2])<<17);
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u32 addr2 = addr & (bl17 | 0xf001ffff);
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u32 batu = (m_MSR.PR ? BATU_Vp : BATU_Vs);
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if (BATU_BEPI(addr2) == BATU_BEPI(PowerPC::ppcState.spr[SPR_DBAT0U + i * 2])) {
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// bat applies to this address
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if (PowerPC::ppcState.spr[SPR_DBAT0U + i * 2] & batu) {
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// bat entry valid
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u32 offset = BAT_EA_OFFSET(addr);
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u32 page = BAT_EA_11(addr);
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page &= ~bl17;
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page |= BATL_BRPN(PowerPC::ppcState.spr[SPR_DBAT0L + i * 2]);
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// fixme: check access rights
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result = page | offset;
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return result;
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}
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}
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bl17 = ~(BATU_BL(PowerPC::ppcState.spr[SPR_IBAT0U + i * 2])<<17);
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addr2 = addr & (bl17 | 0xf001ffff);
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batu = (m_MSR.PR ? BATU_Vp : BATU_Vs);
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if (BATU_BEPI(addr2) == BATU_BEPI(PowerPC::ppcState.spr[SPR_IBAT0U + i * 2])) {
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// bat applies to this address
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if (PowerPC::ppcState.spr[SPR_IBAT0U + i * 2] & batu) {
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// bat entry valid
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u32 offset = BAT_EA_OFFSET(addr);
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u32 page = BAT_EA_11(addr);
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page &= ~bl17;
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page |= BATL_BRPN(PowerPC::ppcState.spr[SPR_IBAT0L + i * 2]);
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// fixme: check access rights
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result = page | offset;
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return result;
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}
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}
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}
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return 0;
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}
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} // namespace
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@ -440,6 +440,7 @@ static OpArg regBuildMemAddress(RegInfo& RI, InstLoc I, InstLoc AI,
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}
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static void regEmitMemLoad(RegInfo& RI, InstLoc I, unsigned Size) {
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bool win32 = false;
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if (RI.UseProfile) {
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unsigned curLoad = ProfiledLoads[RI.numProfiledLoads++];
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if (!(curLoad & 0x0C000000)) {
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@ -460,8 +461,17 @@ static void regEmitMemLoad(RegInfo& RI, InstLoc I, unsigned Size) {
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if (RI.MakeProfile) {
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RI.Jit->MOV(32, M(&ProfiledLoads[RI.numProfiledLoads++]), R(ECX));
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}
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RI.Jit->TEST(32, R(ECX), Imm32(0x0C000000));
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FixupBranch argh = RI.Jit->J_CC(CC_Z);
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#ifdef _M_IX86
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win32 = true;
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#endif
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FixupBranch argh;
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if (!(win32 && Core::GetStartupParameter().iTLBHack == 1))
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{
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RI.Jit->TEST(32, R(ECX), Imm32(0x0C000000));
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argh = RI.Jit->J_CC(CC_Z);
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}
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// Slow safe read using Memory::Read_Ux routines
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#ifdef _M_IX86 // we don't allocate EAX on x64 so no reason to save it.
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if (reg != EAX) {
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RI.Jit->PUSH(32, R(EAX));
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@ -479,10 +489,14 @@ static void regEmitMemLoad(RegInfo& RI, InstLoc I, unsigned Size) {
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RI.Jit->POP(32, R(EAX));
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#endif
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}
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FixupBranch arg2 = RI.Jit->J();
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RI.Jit->SetJumpTarget(argh);
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RI.Jit->UnsafeLoadRegToReg(ECX, reg, Size, 0, false);
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RI.Jit->SetJumpTarget(arg2);
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if (!(win32 && Core::GetStartupParameter().iTLBHack == 1))
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{
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FixupBranch arg2 = RI.Jit->J();
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// Fast unsafe read using memory pointer EBX
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RI.Jit->SetJumpTarget(argh);
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RI.Jit->UnsafeLoadRegToReg(ECX, reg, Size, 0, false);
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RI.Jit->SetJumpTarget(arg2);
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}
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if (regReadUse(RI, I))
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RI.regs[reg] = I;
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}
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@ -1630,4 +1644,4 @@ void ProfiledReJit() {
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DoWriteCode(&jit.ibuild, &jit, true, false);
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jit.js.curBlock->codeSize = (int)(jit.GetCodePtr() - jit.js.rewriteStart);
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jit.GetBlockCache()->FinalizeBlock(jit.js.curBlock->blockNum, jit.jo.enableBlocklink, jit.js.curBlock->normalEntry);
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}
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}
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@ -48,6 +48,7 @@ struct GC_ALIGNED64(PowerPCState)
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u32 pc; // program counter
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u32 npc;
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u32 nextBlock;
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u32 cr; // flags
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u8 cr_fast[8]; // Possibly reorder to 0, 2, 4, 8, 1, 3, 5, 7 so that we can make Compact and Expand super fast?
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@ -65,6 +66,11 @@ struct GC_ALIGNED64(PowerPCState)
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// special purpose registers - controlls quantizers, DMA, and lots of other misc extensions.
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// also for power management, but we don't care about that.
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u32 spr[1024];
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u32 tlb_last;
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u32 tlb_va[16];
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u32 tlb_pa[16];
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InstructionCache iCache;
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};
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Loading…
Reference in New Issue