Merge pull request #2887 from Tilka/swap
Jit64: some byte-swapping changes
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commit
99e88a7af7
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@ -887,21 +887,46 @@ void XEmitter::WriteMOVBE(int bits, u8 op, X64Reg reg, const OpArg& arg)
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void XEmitter::MOVBE(int bits, X64Reg dest, const OpArg& src) {WriteMOVBE(bits, 0xF0, dest, src);}
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void XEmitter::MOVBE(int bits, const OpArg& dest, X64Reg src) {WriteMOVBE(bits, 0xF1, src, dest);}
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void XEmitter::LoadAndSwap(int size, X64Reg dst, const OpArg& src)
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void XEmitter::LoadAndSwap(int size, X64Reg dst, const OpArg& src, bool sign_extend)
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{
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if (cpu_info.bMOVBE)
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switch (size)
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{
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MOVBE(size, dst, src);
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}
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else
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{
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MOV(size, R(dst), src);
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BSWAP(size, dst);
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case 8:
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if (sign_extend)
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MOVSX(32, 8, dst, src);
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else
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MOVZX(32, 8, dst, src);
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break;
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case 16:
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MOVZX(32, 16, dst, src);
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if (sign_extend)
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{
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BSWAP(32, dst);
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SAR(32, R(dst), Imm8(16));
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}
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else
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{
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ROL(16, R(dst), Imm8(8));
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}
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break;
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case 32:
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case 64:
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if (cpu_info.bMOVBE)
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{
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MOVBE(size, dst, src);
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}
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else
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{
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MOV(size, R(dst), src);
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BSWAP(size, dst);
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}
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break;
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}
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}
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void XEmitter::SwapAndStore(int size, const OpArg& dst, X64Reg src)
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u8* XEmitter::SwapAndStore(int size, const OpArg& dst, X64Reg src)
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{
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u8* mov_location = GetWritableCodePtr();
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if (cpu_info.bMOVBE)
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{
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MOVBE(size, dst, src);
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@ -909,8 +934,10 @@ void XEmitter::SwapAndStore(int size, const OpArg& dst, X64Reg src)
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else
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{
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BSWAP(size, src);
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mov_location = GetWritableCodePtr();
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MOV(size, dst, R(src));
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}
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return mov_location;
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}
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@ -480,8 +480,8 @@ public:
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// Available only on Atom or >= Haswell so far. Test with cpu_info.bMOVBE.
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void MOVBE(int bits, X64Reg dest, const OpArg& src);
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void MOVBE(int bits, const OpArg& dest, X64Reg src);
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void LoadAndSwap(int size, X64Reg dst, const OpArg& src);
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void SwapAndStore(int size, const OpArg& dst, X64Reg src);
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void LoadAndSwap(int size, X64Reg dst, const OpArg& src, bool sign_extend = false);
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u8* SwapAndStore(int size, const OpArg& dst, X64Reg src);
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// Available only on AMD >= Phenom or Intel >= Haswell
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void LZCNT(int bits, X64Reg dest, const OpArg& src);
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@ -86,33 +86,35 @@ bool Jitx86Base::BackPatch(u32 emAddress, SContext* ctx)
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// Compute the start and length of the memory operation, including
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// any byteswapping.
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int totalSize;
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int totalSize = info.instructionSize;
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u8 *start = codePtr;
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if (!info.isMemoryWrite)
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{
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int bswapNopCount;
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if (info.byteSwap || info.operandSize == 1)
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bswapNopCount = 0;
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// Check the following BSWAP for REX byte
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else if ((codePtr[info.instructionSize] & 0xF0) == 0x40)
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bswapNopCount = 3;
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else
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bswapNopCount = 2;
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totalSize = info.instructionSize + bswapNopCount;
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if (info.operandSize == 2 && !info.byteSwap)
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// MOVBE and single bytes don't need to be swapped.
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if (!info.byteSwap && info.operandSize > 1)
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{
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// REX
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if ((codePtr[totalSize] & 0xF0) == 0x40)
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totalSize++;
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// BSWAP
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if (codePtr[totalSize] == 0x0F && (codePtr[totalSize + 1] & 0xF8) == 0xC8)
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totalSize += 2;
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if (info.operandSize == 2)
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{
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++totalSize;
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// operand size override
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if (codePtr[totalSize] == 0x66)
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totalSize++;
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// REX
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if ((codePtr[totalSize] & 0xF0) == 0x40)
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totalSize++;
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// SAR/ROL
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_assert_(codePtr[totalSize] == 0xC1 && (codePtr[totalSize + 2] == 0x10 ||
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codePtr[totalSize + 2] == 0x08));
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info.signExtend = (codePtr[totalSize + 1] & 0x10) != 0;
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totalSize += 3;
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}
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if (codePtr[totalSize] != 0xc1 || codePtr[totalSize + 2] != 0x10)
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{
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PanicAlert("BackPatch: didn't find expected shift %p", codePtr);
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return false;
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}
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info.signExtend = (codePtr[totalSize + 1] & 0x10) != 0;
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totalSize += 3;
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}
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}
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else
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@ -120,7 +122,6 @@ bool Jitx86Base::BackPatch(u32 emAddress, SContext* ctx)
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if (info.byteSwap || info.hasImmediate)
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{
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// The instruction is a MOVBE but it failed so the value is still in little-endian byte order.
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totalSize = info.instructionSize;
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}
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else
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{
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@ -146,7 +147,7 @@ bool Jitx86Base::BackPatch(u32 emAddress, SContext* ctx)
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break;
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}
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start = codePtr - bswapSize;
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totalSize = info.instructionSize + bswapSize;
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totalSize += bswapSize;
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}
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}
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@ -24,24 +24,8 @@ void EmuCodeBlock::MemoryExceptionCheck()
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void EmuCodeBlock::UnsafeLoadRegToReg(X64Reg reg_addr, X64Reg reg_value, int accessSize, s32 offset, bool signExtend)
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{
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MOVZX(32, accessSize, reg_value, MComplex(RMEM, reg_addr, SCALE_1, offset));
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if (accessSize == 32)
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{
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BSWAP(32, reg_value);
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}
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else if (accessSize == 16)
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{
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BSWAP(32, reg_value);
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if (signExtend)
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SAR(32, R(reg_value), Imm8(16));
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else
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SHR(32, R(reg_value), Imm8(16));
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}
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else if (signExtend)
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{
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// TODO: bake 8-bit into the original load.
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MOVSX(32, accessSize, reg_value, R(reg_value));
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}
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OpArg src = MComplex(RMEM, reg_addr, SCALE_1, offset);
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LoadAndSwap(accessSize, reg_value, src, signExtend);
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}
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void EmuCodeBlock::UnsafeLoadRegToRegNoSwap(X64Reg reg_addr, X64Reg reg_value, int accessSize, s32 offset, bool signExtend)
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@ -84,34 +68,7 @@ u8 *EmuCodeBlock::UnsafeLoadToReg(X64Reg reg_value, OpArg opAddress, int accessS
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}
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result = GetWritableCodePtr();
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if (accessSize == 8 && signExtend)
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MOVSX(32, accessSize, reg_value, memOperand);
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else
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MOVZX(64, accessSize, reg_value, memOperand);
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switch (accessSize)
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{
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case 8:
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_dbg_assert_(DYNA_REC, BACKPATCH_SIZE - (GetCodePtr() - result <= 0));
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break;
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case 16:
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BSWAP(32, reg_value);
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if (signExtend)
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SAR(32, R(reg_value), Imm8(16));
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else
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SHR(32, R(reg_value), Imm8(16));
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break;
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case 32:
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BSWAP(32, reg_value);
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break;
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case 64:
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BSWAP(64, reg_value);
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break;
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}
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LoadAndSwap(accessSize, reg_value, memOperand, signExtend);
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return result;
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}
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@ -415,17 +372,7 @@ u8 *EmuCodeBlock::UnsafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int acce
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}
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else if (swap)
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{
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if (cpu_info.bMOVBE)
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{
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MOVBE(accessSize, dest, reg_value.GetSimpleReg());
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}
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else
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{
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if (accessSize > 8)
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BSWAP(accessSize, reg_value.GetSimpleReg());
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result = GetWritableCodePtr();
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MOV(accessSize, dest, reg_value);
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}
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result = SwapAndStore(accessSize, dest, reg_value.GetSimpleReg());
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}
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else
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{
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@ -53,21 +53,12 @@ OpArg VertexLoaderX64::GetVertexAddr(int array, u64 attribute)
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OpArg data = MDisp(src_reg, m_src_ofs);
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if (attribute & MASK_INDEXED)
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{
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if (attribute == INDEX8)
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{
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MOVZX(64, 8, scratch1, data);
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m_src_ofs += 1;
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}
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else
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{
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MOV(16, R(scratch1), data);
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m_src_ofs += 2;
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BSWAP(16, scratch1);
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MOVZX(64, 16, scratch1, R(scratch1));
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}
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int bits = attribute == INDEX8 ? 8 : 16;
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LoadAndSwap(bits, scratch1, data);
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m_src_ofs += bits / 8;
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if (array == ARRAY_POSITION)
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{
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CMP(attribute == INDEX8 ? 8 : 16, R(scratch1), Imm8(-1));
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CMP(bits, R(scratch1), Imm8(-1));
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m_skip_vertex = J_CC(CC_E, true);
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}
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IMUL(32, scratch1, MPIC(&g_main_cp_state.array_strides[array]));
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