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Removed the tag check in InvalidateTLBEntry. All four TLB entries are always cleared on each invalidate command. 

Initialised the TLB cache to start from a consistent state on reset.
This commit is contained in:
skidau 2014-12-05 19:56:45 +11:00
parent 693f413364
commit 997681b65a
2 changed files with 35 additions and 32 deletions
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53
Source/Core/Core/HW/MemmapFunctions.cpp
View File

@ -709,14 +709,6 @@ static u32 LookupTLBPageAddress(const XCheckTLBFlag _Flag, const u32 vpa, u32 *p
PowerPC::tlb_entry *tlbe = PowerPC::ppcState.tlb[_Flag == FLAG_OPCODE][(vpa >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK];
if (tlbe[0].tag == (vpa & ~0xfff) && !(tlbe[0].flags & TLB_FLAG_INVALID))
{
if (_Flag != FLAG_NO_EXCEPTION)
{
tlbe[0].flags |= TLB_FLAG_MOST_RECENT;
tlbe[1].flags &= ~TLB_FLAG_MOST_RECENT;
}
*paddr = tlbe[0].paddr | (vpa & 0xfff);
// Check if C bit requires updating
if (_Flag == FLAG_WRITE)
{
@ -727,18 +719,18 @@ static u32 LookupTLBPageAddress(const XCheckTLBFlag _Flag, const u32 vpa, u32 *p
return 0;
}
if (_Flag != FLAG_NO_EXCEPTION)
{
tlbe[0].flags |= TLB_FLAG_MOST_RECENT;
tlbe[1].flags &= ~TLB_FLAG_MOST_RECENT;
}
*paddr = tlbe[0].paddr | (vpa & 0xfff);
return 1;
}
if (tlbe[1].tag == (vpa & ~0xfff) && !(tlbe[1].flags & TLB_FLAG_INVALID))
{
if (_Flag != FLAG_NO_EXCEPTION)
{
tlbe[1].flags |= TLB_FLAG_MOST_RECENT;
tlbe[0].flags &= ~TLB_FLAG_MOST_RECENT;
}
*paddr = tlbe[1].paddr | (vpa & 0xfff);
// Check if C bit requires updating
if (_Flag == FLAG_WRITE)
{
@ -749,6 +741,14 @@ static u32 LookupTLBPageAddress(const XCheckTLBFlag _Flag, const u32 vpa, u32 *p
return 0;
}
if (_Flag != FLAG_NO_EXCEPTION)
{
tlbe[1].flags |= TLB_FLAG_MOST_RECENT;
tlbe[0].flags &= ~TLB_FLAG_MOST_RECENT;
}
*paddr = tlbe[1].paddr | (vpa & 0xfff);
return 1;
}
return 0;
@ -781,23 +781,11 @@ static void UpdateTLBEntry(const XCheckTLBFlag _Flag, UPTE2 PTE2, const u32 vpa,
void InvalidateTLBEntry(u32 vpa)
{
PowerPC::tlb_entry *tlbe = PowerPC::ppcState.tlb[0][(vpa >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK];
if (tlbe[0].tag == (vpa & ~0xfff))
{
tlbe[0].flags |= TLB_FLAG_INVALID;
}
if (tlbe[1].tag == (vpa & ~0xfff))
{
tlbe[1].flags |= TLB_FLAG_INVALID;
}
tlbe[0].flags |= TLB_FLAG_INVALID;
tlbe[1].flags |= TLB_FLAG_INVALID;
PowerPC::tlb_entry *tlbe_i = PowerPC::ppcState.tlb[1][(vpa >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK];
if (tlbe_i[0].tag == (vpa & ~0xfff))
{
tlbe_i[0].flags |= TLB_FLAG_INVALID;
}
if (tlbe_i[1].tag == (vpa & ~0xfff))
{
tlbe_i[1].flags |= TLB_FLAG_INVALID;
}
tlbe_i[0].flags |= TLB_FLAG_INVALID;
tlbe_i[1].flags |= TLB_FLAG_INVALID;
}
// Page Address Translation
@ -869,6 +857,7 @@ static u32 TranslatePageAddress(const u32 _Address, const XCheckTLBFlag _Flag)
UPTE2 PTE2;
PTE2.Hex = bswap((*(u32*)&pRAM[(pteg_addr + 4)]));
// set the access bits
switch (_Flag)
{
case FLAG_READ: PTE2.R = 1; break;

14
Source/Core/Core/PowerPC/PowerPC.cpp
View File

@ -121,6 +121,20 @@ void Init(int cpu_core)
ppcState.pagetable_base = 0;
ppcState.pagetable_hashmask = 0;
for (int tlb = 0; tlb < 2; tlb++)
{
for (int set = 0; set < 64; set++)
{
for (int way = 0; way < 2; way++)
{
ppcState.tlb[tlb][set][way].flags = TLB_FLAG_INVALID;
ppcState.tlb[tlb][set][way].paddr = 0;
ppcState.tlb[tlb][set][way].pteg = 0;
ppcState.tlb[tlb][set][way].tag = 0;
}
}
}
ResetRegisters();
PPCTables::InitTables(cpu_core);