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Core: Fix warnings in JitRegCache

This commit is contained in:
Lioncash 2014-07-18 01:17:58 -04:00
parent ae65b3ba2c
commit 98f352a4e6
2 changed files with 51 additions and 47 deletions
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52
Source/Core/Core/PowerPC/Jit64/JitRegCache.cpp
View File

@ -2,6 +2,8 @@
// Licensed under GPLv2 // Licensed under GPLv2
// Refer to the license.txt file included. // Refer to the license.txt file included.
#include <cinttypes>
#include "Core/PowerPC/Jit64/Jit.h" #include "Core/PowerPC/Jit64/Jit.h"
#include "Core/PowerPC/Jit64/JitAsm.h" #include "Core/PowerPC/Jit64/JitAsm.h"
#include "Core/PowerPC/Jit64/JitRegCache.h" #include "Core/PowerPC/Jit64/JitRegCache.h"
@ -20,7 +22,7 @@ void RegCache::Start()
xreg.free = true; xreg.free = true;
xreg.dirty = false; xreg.dirty = false;
xreg.locked = false; xreg.locked = false;
xreg.ppcReg = -1; xreg.ppcReg = INVALID_REG;
} }
for (size_t i = 0; i < regs.size(); i++) for (size_t i = 0; i < regs.size(); i++)
{ {
@ -81,9 +83,9 @@ void RegCache::UnlockAllX()
X64Reg RegCache::GetFreeXReg() X64Reg RegCache::GetFreeXReg()
{ {
int aCount; size_t aCount;
const int* aOrder = GetAllocationOrder(aCount); const int* aOrder = GetAllocationOrder(aCount);
for (int i = 0; i < aCount; i++) for (size_t i = 0; i < aCount; i++)
{ {
X64Reg xr = (X64Reg)aOrder[i]; X64Reg xr = (X64Reg)aOrder[i];
if (!xregs[xr].locked && xregs[xr].free) if (!xregs[xr].locked && xregs[xr].free)
@ -94,12 +96,12 @@ X64Reg RegCache::GetFreeXReg()
//Okay, not found :( Force grab one //Okay, not found :( Force grab one
//TODO - add a pass to grab xregs whose ppcreg is not used in the next 3 instructions //TODO - add a pass to grab xregs whose ppcreg is not used in the next 3 instructions
for (int i = 0; i < aCount; i++) for (size_t i = 0; i < aCount; i++)
{ {
X64Reg xr = (X64Reg)aOrder[i]; X64Reg xr = (X64Reg)aOrder[i];
if (xregs[xr].locked) if (xregs[xr].locked)
continue; continue;
int preg = xregs[xr].ppcReg; size_t preg = xregs[xr].ppcReg;
if (!regs[preg].locked) if (!regs[preg].locked)
{ {
StoreFromRegister(preg); StoreFromRegister(preg);
@ -108,7 +110,7 @@ X64Reg RegCache::GetFreeXReg()
} }
//Still no dice? Die! //Still no dice? Die!
_assert_msg_(DYNA_REC, 0, "Regcache ran out of regs"); _assert_msg_(DYNA_REC, 0, "Regcache ran out of regs");
return (X64Reg) -1; return INVALID_REG;
} }
void RegCache::FlushR(X64Reg reg) void RegCache::FlushR(X64Reg reg)
@ -136,34 +138,36 @@ int RegCache::SanityCheck() const
return 2; return 2;
} }
else if (regs[i].location.IsImm()) else if (regs[i].location.IsImm())
{
return 3; return 3;
} }
} }
}
return 0; return 0;
} }
void RegCache::DiscardRegContentsIfCached(int preg) void RegCache::DiscardRegContentsIfCached(size_t preg)
{ {
if (IsBound(preg)) if (IsBound(preg))
{ {
X64Reg xr = regs[preg].location.GetSimpleReg(); X64Reg xr = regs[preg].location.GetSimpleReg();
xregs[xr].free = true; xregs[xr].free = true;
xregs[xr].dirty = false; xregs[xr].dirty = false;
xregs[xr].ppcReg = -1; xregs[xr].ppcReg = INVALID_REG;
regs[preg].away = false; regs[preg].away = false;
regs[preg].location = GetDefaultLocation(preg); regs[preg].location = GetDefaultLocation(preg);
} }
} }
void GPRRegCache::SetImmediate32(int preg, u32 immValue) void GPRRegCache::SetImmediate32(size_t preg, u32 immValue)
{ {
DiscardRegContentsIfCached(preg); DiscardRegContentsIfCached(preg);
regs[preg].away = true; regs[preg].away = true;
regs[preg].location = Imm32(immValue); regs[preg].location = Imm32(immValue);
} }
const int *GPRRegCache::GetAllocationOrder(int &count) const int* GPRRegCache::GetAllocationOrder(size_t& count)
{ {
static const int allocationOrder[] = static const int allocationOrder[] =
{ {
@ -182,7 +186,7 @@ const int *GPRRegCache::GetAllocationOrder(int &count)
return allocationOrder; return allocationOrder;
} }
const int *FPURegCache::GetAllocationOrder(int &count) const int* FPURegCache::GetAllocationOrder(size_t& count)
{ {
static const int allocationOrder[] = static const int allocationOrder[] =
{ {
@ -196,17 +200,17 @@ const int *FPURegCache::GetAllocationOrder(int &count)
return allocationOrder; return allocationOrder;
} }
OpArg GPRRegCache::GetDefaultLocation(int reg) const OpArg GPRRegCache::GetDefaultLocation(size_t reg) const
{ {
return M(&ppcState.gpr[reg]); return M(&ppcState.gpr[reg]);
} }
OpArg FPURegCache::GetDefaultLocation(int reg) const OpArg FPURegCache::GetDefaultLocation(size_t reg) const
{ {
return M(&ppcState.ps[reg][0]); return M(&ppcState.ps[reg][0]);
} }
void RegCache::KillImmediate(int preg, bool doLoad, bool makeDirty) void RegCache::KillImmediate(size_t preg, bool doLoad, bool makeDirty)
{ {
if (regs[preg].away) if (regs[preg].away)
{ {
@ -217,7 +221,7 @@ void RegCache::KillImmediate(int preg, bool doLoad, bool makeDirty)
} }
} }
void RegCache::BindToRegister(int i, bool doLoad, bool makeDirty) void RegCache::BindToRegister(size_t i, bool doLoad, bool makeDirty)
{ {
if (!regs[i].away && regs[i].location.IsImm()) if (!regs[i].away && regs[i].location.IsImm())
PanicAlert("Bad immediate"); PanicAlert("Bad immediate");
@ -232,7 +236,7 @@ void RegCache::BindToRegister(int i, bool doLoad, bool makeDirty)
xregs[xr].dirty = makeDirty || regs[i].location.IsImm(); xregs[xr].dirty = makeDirty || regs[i].location.IsImm();
if (doLoad) if (doLoad)
LoadRegister(i, xr); LoadRegister(i, xr);
for (int j = 0; j < (int)regs.size(); j++) for (size_t j = 0; j < regs.size(); j++)
{ {
if (i != j && regs[j].location.IsSimpleReg() && regs[j].location.GetSimpleReg() == xr) if (i != j && regs[j].location.IsSimpleReg() && regs[j].location.GetSimpleReg() == xr)
{ {
@ -255,7 +259,7 @@ void RegCache::BindToRegister(int i, bool doLoad, bool makeDirty)
} }
} }
void RegCache::StoreFromRegister(int i, FlushMode mode) void RegCache::StoreFromRegister(size_t i, FlushMode mode)
{ {
if (regs[i].away) if (regs[i].away)
{ {
@ -267,7 +271,7 @@ void RegCache::StoreFromRegister(int i, FlushMode mode)
if (mode == FLUSH_ALL) if (mode == FLUSH_ALL)
{ {
xregs[xr].free = true; xregs[xr].free = true;
xregs[xr].ppcReg = -1; xregs[xr].ppcReg = INVALID_REG;
xregs[xr].dirty = false; xregs[xr].dirty = false;
} }
} }
@ -287,17 +291,17 @@ void RegCache::StoreFromRegister(int i, FlushMode mode)
} }
} }
void GPRRegCache::LoadRegister(int preg, X64Reg newLoc) void GPRRegCache::LoadRegister(size_t preg, X64Reg newLoc)
{ {
emit->MOV(32, ::Gen::R(newLoc), regs[preg].location); emit->MOV(32, ::Gen::R(newLoc), regs[preg].location);
} }
void GPRRegCache::StoreRegister(int preg, OpArg newLoc) void GPRRegCache::StoreRegister(size_t preg, OpArg newLoc)
{ {
emit->MOV(32, newLoc, regs[preg].location); emit->MOV(32, newLoc, regs[preg].location);
} }
void FPURegCache::LoadRegister(int preg, X64Reg newLoc) void FPURegCache::LoadRegister(size_t preg, X64Reg newLoc)
{ {
if (!regs[preg].location.IsImm() && (regs[preg].location.offset & 0xF)) if (!regs[preg].location.IsImm() && (regs[preg].location.offset & 0xF))
{ {
@ -306,7 +310,7 @@ void FPURegCache::LoadRegister(int preg, X64Reg newLoc)
emit->MOVAPD(newLoc, regs[preg].location); emit->MOVAPD(newLoc, regs[preg].location);
} }
void FPURegCache::StoreRegister(int preg, OpArg newLoc) void FPURegCache::StoreRegister(size_t preg, OpArg newLoc)
{ {
emit->MOVAPD(newLoc, regs[preg].location.GetSimpleReg()); emit->MOVAPD(newLoc, regs[preg].location.GetSimpleReg());
} }
@ -323,7 +327,7 @@ void RegCache::Flush(FlushMode mode)
{ {
if (regs[i].locked) if (regs[i].locked)
{ {
PanicAlert("Someone forgot to unlock PPC reg %zu (X64 reg %i).", i, RX(i)); PanicAlert("Someone forgot to unlock PPC reg %" PRIx64 " (X64 reg %i).", i, RX(i));
} }
if (regs[i].away) if (regs[i].away)
{ {
@ -333,7 +337,7 @@ void RegCache::Flush(FlushMode mode)
} }
else else
{ {
_assert_msg_(DYNA_REC,0,"Jit64 - Flush unhandled case, reg %zu PC: %08x", i, PC); _assert_msg_(DYNA_REC,0,"Jit64 - Flush unhandled case, reg %" PRIx64 " PC: %08x", i, PC);
} }
} }
} }

44
Source/Core/Core/PowerPC/Jit64/JitRegCache.h
View File

@ -25,7 +25,7 @@ struct PPCCachedReg
struct X64CachedReg struct X64CachedReg
{ {
int ppcReg; size_t ppcReg;
bool dirty; bool dirty;
bool free; bool free;
bool locked; bool locked;
@ -46,7 +46,7 @@ protected:
std::array<PPCCachedReg, 32> regs; std::array<PPCCachedReg, 32> regs;
std::array<X64CachedReg, NUMXREGS> xregs; std::array<X64CachedReg, NUMXREGS> xregs;
virtual const int *GetAllocationOrder(int &count) = 0; virtual const int *GetAllocationOrder(size_t& count) = 0;
XEmitter *emit; XEmitter *emit;
@ -56,7 +56,7 @@ public:
virtual ~RegCache() {} virtual ~RegCache() {}
void Start(); void Start();
void DiscardRegContentsIfCached(int preg); void DiscardRegContentsIfCached(size_t preg);
void SetEmitter(XEmitter *emitter) {emit = emitter;} void SetEmitter(XEmitter *emitter) {emit = emitter;}
void FlushR(X64Reg reg); void FlushR(X64Reg reg);
@ -72,24 +72,24 @@ public:
void Flush(FlushMode mode = FLUSH_ALL); void Flush(FlushMode mode = FLUSH_ALL);
void Flush(PPCAnalyst::CodeOp *op) {Flush();} void Flush(PPCAnalyst::CodeOp *op) {Flush();}
int SanityCheck() const; int SanityCheck() const;
void KillImmediate(int preg, bool doLoad, bool makeDirty); void KillImmediate(size_t preg, bool doLoad, bool makeDirty);
//TODO - instead of doload, use "read", "write" //TODO - instead of doload, use "read", "write"
//read only will not set dirty flag //read only will not set dirty flag
void BindToRegister(int preg, bool doLoad = true, bool makeDirty = true); void BindToRegister(size_t preg, bool doLoad = true, bool makeDirty = true);
void StoreFromRegister(int preg, FlushMode mode = FLUSH_ALL); void StoreFromRegister(size_t preg, FlushMode mode = FLUSH_ALL);
virtual void StoreRegister(int preg, OpArg newLoc) = 0; virtual void StoreRegister(size_t preg, OpArg newLoc) = 0;
virtual void LoadRegister(int preg, X64Reg newLoc) = 0; virtual void LoadRegister(size_t preg, X64Reg newLoc) = 0;
const OpArg &R(int preg) const {return regs[preg].location;} const OpArg &R(size_t preg) const {return regs[preg].location;}
X64Reg RX(int preg) const X64Reg RX(size_t preg) const
{ {
if (IsBound(preg)) if (IsBound(preg))
return regs[preg].location.GetSimpleReg(); return regs[preg].location.GetSimpleReg();
PanicAlert("Not so simple - %i", preg); PanicAlert("Not so simple - %i", preg);
return (X64Reg)-1; return (X64Reg)-1;
} }
virtual OpArg GetDefaultLocation(int reg) const = 0; virtual OpArg GetDefaultLocation(size_t reg) const = 0;
// Register locking. // Register locking.
void Lock(int p1, int p2=0xff, int p3=0xff, int p4=0xff); void Lock(int p1, int p2=0xff, int p3=0xff, int p4=0xff);
@ -97,12 +97,12 @@ public:
void UnlockAll(); void UnlockAll();
void UnlockAllX(); void UnlockAllX();
bool IsFreeX(int xreg) const bool IsFreeX(size_t xreg) const
{ {
return xregs[xreg].free && !xregs[xreg].locked; return xregs[xreg].free && !xregs[xreg].locked;
} }
bool IsBound(int preg) const bool IsBound(size_t preg) const
{ {
return regs[preg].away && regs[preg].location.IsSimpleReg(); return regs[preg].away && regs[preg].location.IsSimpleReg();
} }
@ -114,19 +114,19 @@ public:
class GPRRegCache : public RegCache class GPRRegCache : public RegCache
{ {
public: public:
void StoreRegister(int preg, OpArg newLoc) override; void StoreRegister(size_t preg, OpArg newLoc) override;
void LoadRegister(int preg, X64Reg newLoc) override; void LoadRegister(size_t preg, X64Reg newLoc) override;
OpArg GetDefaultLocation(int reg) const override; OpArg GetDefaultLocation(size_t reg) const override;
const int *GetAllocationOrder(int &count) override; const int* GetAllocationOrder(size_t& count) override;
void SetImmediate32(int preg, u32 immValue); void SetImmediate32(size_t preg, u32 immValue);
}; };
class FPURegCache : public RegCache class FPURegCache : public RegCache
{ {
public: public:
void StoreRegister(int preg, OpArg newLoc) override; void StoreRegister(size_t preg, OpArg newLoc) override;
void LoadRegister(int preg, X64Reg newLoc) override; void LoadRegister(size_t preg, X64Reg newLoc) override;
const int *GetAllocationOrder(int &count) override; const int* GetAllocationOrder(size_t& count) override;
OpArg GetDefaultLocation(int reg) const override; OpArg GetDefaultLocation(size_t reg) const override;
}; };