Merge pull request #4386 from degasus/master
JitArm64: Drop two DUP() usages.
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commit
98389121e6
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@ -85,13 +85,10 @@ void JitArm64::ps_mulsX(UGeckoInstruction inst)
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ARM64Reg VA = fpr.R(a, type);
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ARM64Reg VA = fpr.R(a, type);
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ARM64Reg VC = fpr.R(c, type);
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ARM64Reg VC = fpr.R(c, type);
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ARM64Reg VD = fpr.RW(d, type);
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ARM64Reg VD = fpr.RW(d, type);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.DUP(size, reg_encoder(V0), reg_encoder(VC), upper ? 1 : 0);
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m_float_emit.FMUL(size, reg_encoder(VD), reg_encoder(VA), reg_encoder(VC), upper ? 1 : 0);
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m_float_emit.FMUL(size, reg_encoder(VD), reg_encoder(VA), reg_encoder(V0));
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fpr.FixSinglePrecision(d);
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fpr.FixSinglePrecision(d);
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fpr.Unlock(V0);
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}
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}
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void JitArm64::ps_maddXX(UGeckoInstruction inst)
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void JitArm64::ps_maddXX(UGeckoInstruction inst)
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@ -121,13 +118,11 @@ void JitArm64::ps_maddXX(UGeckoInstruction inst)
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switch (op5)
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switch (op5)
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{
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{
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case 14: // ps_madds0
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case 14: // ps_madds0
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m_float_emit.DUP(size, V0, VC, 0);
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m_float_emit.FMUL(size, V0, VA, VC, 0);
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m_float_emit.FMUL(size, V0, V0, VA);
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m_float_emit.FADD(size, VD, V0, VB);
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m_float_emit.FADD(size, VD, V0, VB);
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break;
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break;
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case 15: // ps_madds1
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case 15: // ps_madds1
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m_float_emit.DUP(size, V0, VC, 1);
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m_float_emit.FMUL(size, V0, VA, VC, 1);
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m_float_emit.FMUL(size, V0, V0, VA);
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m_float_emit.FADD(size, VD, V0, VB);
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m_float_emit.FADD(size, VD, V0, VB);
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break;
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break;
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case 28: // ps_msub
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case 28: // ps_msub
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