Merge pull request #746 from FioraAeterna/fastermtcrf
Improve performance of CR functions in JIT64
This commit is contained in:
commit
961c1db116
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@ -105,8 +105,8 @@ public:
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// Reads a given bit of a given CR register part. Clobbers ABI_PARAM1,
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// Reads a given bit of a given CR register part. Clobbers ABI_PARAM1,
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// don't forget to xlock it before.
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// don't forget to xlock it before.
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void GetCRFieldBit(int field, int bit, Gen::X64Reg out);
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void GetCRFieldBit(int field, int bit, Gen::X64Reg out, bool negate = false);
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// Clobbers ABI_PARAM1 and ABI_PARAM2, xlock them before.
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// Clobbers ABI_PARAM1, xlock it before.
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void SetCRFieldBit(int field, int bit, Gen::X64Reg in);
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void SetCRFieldBit(int field, int bit, Gen::X64Reg in);
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// Generates a branch that will check if a given bit of a CR register part
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// Generates a branch that will check if a given bit of a CR register part
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@ -11,31 +11,28 @@
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using namespace Gen;
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using namespace Gen;
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void Jit64::GetCRFieldBit(int field, int bit, Gen::X64Reg out)
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void Jit64::GetCRFieldBit(int field, int bit, Gen::X64Reg out, bool negate)
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{
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{
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switch (bit)
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switch (bit)
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{
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{
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case CR_SO_BIT: // check bit 61 set
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case CR_SO_BIT: // check bit 61 set
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 61));
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BT(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(61));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(ABI_PARAM1));
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SETcc(negate ? CC_NC : CC_C, R(out));
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SETcc(CC_NZ, R(out));
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break;
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break;
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case CR_EQ_BIT: // check bits 31-0 == 0
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case CR_EQ_BIT: // check bits 31-0 == 0
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CMP(32, M(&PowerPC::ppcState.cr_val[field]), Imm32(0));
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CMP(32, M(&PowerPC::ppcState.cr_val[field]), Imm8(0));
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SETcc(CC_Z, R(out));
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SETcc(negate ? CC_NZ : CC_Z, R(out));
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break;
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break;
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case CR_GT_BIT: // check val > 0
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case CR_GT_BIT: // check val > 0
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MOV(64, R(ABI_PARAM1), M(&PowerPC::ppcState.cr_val[field]));
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CMP(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(0));
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TEST(64, R(ABI_PARAM1), R(ABI_PARAM1));
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SETcc(negate ? CC_NG : CC_G, R(out));
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SETcc(CC_G, R(out));
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break;
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break;
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case CR_LT_BIT: // check bit 62 set
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case CR_LT_BIT: // check bit 62 set
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 62));
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BT(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(62));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(ABI_PARAM1));
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SETcc(negate ? CC_NC : CC_C, R(out));
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SETcc(CC_NZ, R(out));
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break;
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break;
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default:
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default:
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@ -45,63 +42,40 @@ void Jit64::GetCRFieldBit(int field, int bit, Gen::X64Reg out)
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void Jit64::SetCRFieldBit(int field, int bit, Gen::X64Reg in)
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void Jit64::SetCRFieldBit(int field, int bit, Gen::X64Reg in)
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{
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{
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MOV(64, R(ABI_PARAM2), M(&PowerPC::ppcState.cr_val[field]));
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MOV(64, R(ABI_PARAM1), M(&PowerPC::ppcState.cr_val[field]));
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TEST(8, R(in), Imm8(1));
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MOVZX(32, 8, in, R(in));
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FixupBranch input_is_set = J_CC(CC_NZ, false);
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// New value is 0.
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switch (bit)
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{
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case CR_SO_BIT: // unset bit 61
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MOV(64, R(ABI_PARAM1), Imm64(~(1ull << 61)));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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case CR_EQ_BIT: // set bit 0 to 1
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OR(8, R(ABI_PARAM2), Imm8(1));
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break;
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case CR_GT_BIT: // !GT, set bit 63
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 63));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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case CR_LT_BIT: // !LT, unset bit 62
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MOV(64, R(ABI_PARAM1), Imm64(~(1ull << 62)));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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}
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FixupBranch end = J();
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SetJumpTarget(input_is_set);
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switch (bit)
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switch (bit)
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{
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{
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case CR_SO_BIT: // set bit 61
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case CR_SO_BIT: // set bit 61 to input
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 61));
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BTR(64, R(ABI_PARAM1), Imm8(61));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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SHL(64, R(in), Imm8(61));
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OR(64, R(ABI_PARAM1), R(in));
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break;
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break;
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case CR_EQ_BIT: // set bits 31-0 to 0
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case CR_EQ_BIT: // clear low 32 bits, set bit 0 to !input
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MOV(64, R(ABI_PARAM1), Imm64(0xFFFFFFFF00000000));
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SHR(64, R(ABI_PARAM1), Imm8(32));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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SHL(64, R(ABI_PARAM1), Imm8(32));
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XOR(32, R(in), Imm8(1));
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OR(64, R(ABI_PARAM1), R(in));
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break;
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break;
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case CR_GT_BIT: // unset bit 63
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case CR_GT_BIT: // set bit 63 to !input
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MOV(64, R(ABI_PARAM1), Imm64(~(1ull << 63)));
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BTR(64, R(ABI_PARAM1), Imm8(63));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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NOT(32, R(in));
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SHL(64, R(in), Imm8(63));
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OR(64, R(ABI_PARAM1), R(in));
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break;
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break;
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case CR_LT_BIT: // set bit 62
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case CR_LT_BIT: // set bit 62 to input
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 62));
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BTR(64, R(ABI_PARAM1), Imm8(62));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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SHL(64, R(in), Imm8(62));
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OR(64, R(ABI_PARAM1), R(in));
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break;
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break;
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}
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}
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SetJumpTarget(end);
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BTS(64, R(ABI_PARAM1), Imm8(32));
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 32));
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MOV(64, M(&PowerPC::ppcState.cr_val[field]), R(ABI_PARAM1));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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MOV(64, M(&PowerPC::ppcState.cr_val[field]), R(ABI_PARAM2));
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}
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}
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FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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@ -109,23 +83,20 @@ FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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switch (bit)
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switch (bit)
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{
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{
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case CR_SO_BIT: // check bit 61 set
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case CR_SO_BIT: // check bit 61 set
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MOV(64, R(RAX), Imm64(1ull << 61));
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BT(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(61));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(RAX));
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return J_CC(jump_if_set ? CC_C : CC_NC, true);
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return J_CC(jump_if_set ? CC_NZ : CC_Z, true);
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case CR_EQ_BIT: // check bits 31-0 == 0
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case CR_EQ_BIT: // check bits 31-0 == 0
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CMP(32, M(&PowerPC::ppcState.cr_val[field]), Imm32(0));
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CMP(32, M(&PowerPC::ppcState.cr_val[field]), Imm8(0));
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return J_CC(jump_if_set ? CC_Z : CC_NZ, true);
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return J_CC(jump_if_set ? CC_Z : CC_NZ, true);
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case CR_GT_BIT: // check val > 0
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case CR_GT_BIT: // check val > 0
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MOV(64, R(RAX), M(&PowerPC::ppcState.cr_val[field]));
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CMP(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(0));
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TEST(64, R(RAX), R(RAX));
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return J_CC(jump_if_set ? CC_G : CC_LE, true);
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return J_CC(jump_if_set ? CC_G : CC_LE, true);
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case CR_LT_BIT: // check bit 62 set
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case CR_LT_BIT: // check bit 62 set
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MOV(64, R(RAX), Imm64(1ull << 62));
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BT(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(62));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(RAX));
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return J_CC(jump_if_set ? CC_C : CC_NC, true);
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return J_CC(jump_if_set ? CC_NZ : CC_Z, true);
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default:
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default:
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_assert_msg_(DYNA_REC, false, "Invalid CR bit");
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_assert_msg_(DYNA_REC, false, "Invalid CR bit");
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@ -277,51 +248,51 @@ void Jit64::mfcr(UGeckoInstruction inst)
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JITDISABLE(bJITSystemRegistersOff);
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JITDISABLE(bJITSystemRegistersOff);
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// USES_CR
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// USES_CR
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int d = inst.RD;
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int d = inst.RD;
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gpr.Lock(d);
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gpr.BindToRegister(d, false, true);
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gpr.KillImmediate(d, false, true);
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XOR(32, gpr.R(d), gpr.R(d));
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XOR(32, R(EAX), R(EAX));
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gpr.FlushLockX(ABI_PARAM1, ABI_PARAM2);
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gpr.FlushLockX(ABI_PARAM1);
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X64Reg cr_val = ABI_PARAM1;
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X64Reg cr_val = ABI_PARAM1;
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X64Reg tmp = ABI_PARAM2;
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// we only need to zero the high bits of EAX once
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XOR(32, R(EAX), R(EAX));
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for (int i = 0; i < 8; i++)
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for (int i = 0; i < 8; i++)
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{
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{
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static const u8 m_flagTable[8] = {0x0,0x1,0x8,0x9,0x0,0x1,0x8,0x9};
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if (i != 0)
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if (i != 0)
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SHL(32, R(EAX), Imm8(4));
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SHL(32, gpr.R(d), Imm8(4));
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MOV(64, R(cr_val), M(&PowerPC::ppcState.cr_val[i]));
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MOV(64, R(cr_val), M(&PowerPC::ppcState.cr_val[i]));
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// SO: Bit 61 set.
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// EQ: Bits 31-0 == 0; set flag bit 1
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MOV(64, R(tmp), R(cr_val));
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SHR(64, R(tmp), Imm8(61));
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AND(32, R(tmp), Imm8(1));
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OR(32, R(EAX), R(tmp));
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// EQ: Bits 31-0 == 0.
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XOR(32, R(tmp), R(tmp));
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TEST(32, R(cr_val), R(cr_val));
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TEST(32, R(cr_val), R(cr_val));
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SETcc(CC_Z, R(tmp));
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SETcc(CC_Z, R(EAX));
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SHL(32, R(tmp), Imm8(1));
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LEA(32, gpr.RX(d), MComplex(gpr.RX(d), EAX, SCALE_2, 0));
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OR(32, R(EAX), R(tmp));
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// GT: Value > 0.
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// GT: Value > 0; set flag bit 2
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TEST(64, R(cr_val), R(cr_val));
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TEST(64, R(cr_val), R(cr_val));
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SETcc(CC_G, R(tmp));
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SETcc(CC_G, R(EAX));
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SHL(32, R(tmp), Imm8(2));
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LEA(32, gpr.RX(d), MComplex(gpr.RX(d), EAX, SCALE_4, 0));
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OR(32, R(EAX), R(tmp));
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// LT: Bit 62 set.
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// SO: Bit 61 set; set flag bit 0
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MOV(64, R(tmp), R(cr_val));
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// LT: Bit 62 set; set flag bit 3
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SHR(64, R(tmp), Imm8(62 - 3));
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SHR(64, R(cr_val), Imm8(61));
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AND(32, R(tmp), Imm8(0x8));
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MOVZX(32, 8, EAX, MDisp(cr_val, (u32)(u64)m_flagTable));
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OR(32, R(EAX), R(tmp));
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OR(32, gpr.R(d), R(EAX));
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}
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}
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MOV(32, gpr.R(d), R(EAX));
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gpr.UnlockAll();
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gpr.UnlockAll();
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gpr.UnlockAllX();
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gpr.UnlockAllX();
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}
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}
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// convert flags into 64-bit CR values with a lookup table
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static const u64 m_crTable[16] =
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{
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PPCCRToInternal(0x0), PPCCRToInternal(0x1), PPCCRToInternal(0x2), PPCCRToInternal(0x3),
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PPCCRToInternal(0x4), PPCCRToInternal(0x5), PPCCRToInternal(0x6), PPCCRToInternal(0x7),
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PPCCRToInternal(0x8), PPCCRToInternal(0x9), PPCCRToInternal(0xA), PPCCRToInternal(0xB),
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PPCCRToInternal(0xC), PPCCRToInternal(0xD), PPCCRToInternal(0xE), PPCCRToInternal(0xF),
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};
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void Jit64::mtcrf(UGeckoInstruction inst)
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void Jit64::mtcrf(UGeckoInstruction inst)
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{
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{
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INSTRUCTION_START
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INSTRUCTION_START
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@ -338,8 +309,16 @@ void Jit64::mtcrf(UGeckoInstruction inst)
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if ((crm & (0x80 >> i)) != 0)
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if ((crm & (0x80 >> i)) != 0)
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{
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{
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u8 newcr = (gpr.R(inst.RS).offset >> (28 - (i * 4))) & 0xF;
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u8 newcr = (gpr.R(inst.RS).offset >> (28 - (i * 4))) & 0xF;
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MOV(64, R(RAX), Imm64(PPCCRToInternal(newcr)));
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u64 newcrval = PPCCRToInternal(newcr);
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MOV(64, M(&PowerPC::ppcState.cr_val[i]), R(RAX));
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if ((s64)newcrval == (s32)newcrval)
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{
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MOV(64, M(&PowerPC::ppcState.cr_val[i]), Imm32(newcrval));
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}
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else
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{
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MOV(64, R(RAX), Imm64(newcrval));
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MOV(64, M(&PowerPC::ppcState.cr_val[i]), R(RAX));
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}
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}
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}
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}
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}
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}
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}
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@ -347,50 +326,20 @@ void Jit64::mtcrf(UGeckoInstruction inst)
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{
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{
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gpr.Lock(inst.RS);
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gpr.Lock(inst.RS);
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gpr.BindToRegister(inst.RS, true, false);
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gpr.BindToRegister(inst.RS, true, false);
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gpr.FlushLockX(ABI_PARAM1, ABI_PARAM2);
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for (int i = 0; i < 8; i++)
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for (int i = 0; i < 8; i++)
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{
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{
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if ((crm & (0x80 >> i)) != 0)
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if ((crm & (0x80 >> i)) != 0)
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{
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{
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MOVZX(64, 32, EAX, gpr.R(inst.RS));
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MOV(32, R(EAX), gpr.R(inst.RS));
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SHR(64, R(EAX), Imm8(28 - (i * 4)));
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if (i != 7)
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AND(64, R(EAX), Imm32(0xF));
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SHR(32, R(EAX), Imm8(28 - (i * 4)));
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if (i != 0)
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X64Reg cr_val = ABI_PARAM1;
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AND(32, R(EAX), Imm8(0xF));
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X64Reg tmp = ABI_PARAM2;
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MOV(64, R(EAX), MScaled(EAX, SCALE_8, (u32)(u64)m_crTable));
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MOV(64, M(&PowerPC::ppcState.cr_val[i]), R(EAX));
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MOV(64, R(cr_val), Imm64(1ull << 32));
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// SO
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MOV(64, R(tmp), R(EAX));
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SHL(64, R(tmp), Imm8(63));
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SHR(64, R(tmp), Imm8(63 - 61));
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OR(64, R(cr_val), R(tmp));
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// EQ
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MOV(64, R(tmp), R(EAX));
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NOT(64, R(tmp));
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AND(64, R(tmp), Imm8(CR_EQ));
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OR(64, R(cr_val), R(tmp));
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// GT
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MOV(64, R(tmp), R(EAX));
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NOT(64, R(tmp));
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AND(64, R(tmp), Imm8(CR_GT));
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SHL(64, R(tmp), Imm8(63 - 2));
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OR(64, R(cr_val), R(tmp));
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// LT
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MOV(64, R(tmp), R(EAX));
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AND(64, R(tmp), Imm8(CR_LT));
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SHL(64, R(tmp), Imm8(62 - 3));
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OR(64, R(cr_val), R(tmp));
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MOV(64, M(&PowerPC::ppcState.cr_val[i]), R(cr_val));
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||||||
}
|
}
|
||||||
}
|
}
|
||||||
gpr.UnlockAll();
|
gpr.UnlockAll();
|
||||||
gpr.UnlockAllX();
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -416,41 +365,11 @@ void Jit64::mcrxr(UGeckoInstruction inst)
|
||||||
// USES_CR
|
// USES_CR
|
||||||
|
|
||||||
// Copy XER[0-3] into CR[inst.CRFD]
|
// Copy XER[0-3] into CR[inst.CRFD]
|
||||||
MOVZX(64, 32, EAX, M(&PowerPC::ppcState.spr[SPR_XER]));
|
MOV(32, R(EAX), M(&PowerPC::ppcState.spr[SPR_XER]));
|
||||||
SHR(64, R(EAX), Imm8(28));
|
SHR(32, R(EAX), Imm8(28));
|
||||||
|
|
||||||
gpr.FlushLockX(ABI_PARAM1, ABI_PARAM2);
|
MOV(64, R(EAX), MScaled(EAX, SCALE_8, (u32)(u64)m_crTable));
|
||||||
X64Reg cr_val = ABI_PARAM1;
|
MOV(64, M(&PowerPC::ppcState.cr_val[inst.CRFD]), R(EAX));
|
||||||
X64Reg tmp = ABI_PARAM2;
|
|
||||||
|
|
||||||
MOV(64, R(cr_val), Imm64(1ull << 32));
|
|
||||||
|
|
||||||
// SO
|
|
||||||
MOV(64, R(tmp), R(EAX));
|
|
||||||
SHL(64, R(tmp), Imm8(63));
|
|
||||||
SHR(64, R(tmp), Imm8(63 - 61));
|
|
||||||
OR(64, R(cr_val), R(tmp));
|
|
||||||
|
|
||||||
// EQ
|
|
||||||
MOV(64, R(tmp), R(EAX));
|
|
||||||
AND(64, R(tmp), Imm8(0x2));
|
|
||||||
OR(64, R(cr_val), R(tmp));
|
|
||||||
|
|
||||||
// GT
|
|
||||||
MOV(64, R(tmp), R(EAX));
|
|
||||||
NOT(64, R(tmp));
|
|
||||||
AND(64, R(tmp), Imm8(0x4));
|
|
||||||
SHL(64, R(tmp), Imm8(63 - 2));
|
|
||||||
OR(64, R(cr_val), R(tmp));
|
|
||||||
|
|
||||||
// LT
|
|
||||||
MOV(64, R(tmp), R(EAX));
|
|
||||||
AND(64, R(tmp), Imm8(0x8));
|
|
||||||
SHL(64, R(tmp), Imm8(62 - 3));
|
|
||||||
OR(64, R(cr_val), R(tmp));
|
|
||||||
|
|
||||||
MOV(64, M(&PowerPC::ppcState.cr_val[inst.CRFD]), R(cr_val));
|
|
||||||
gpr.UnlockAllX();
|
|
||||||
|
|
||||||
// Clear XER[0-3]
|
// Clear XER[0-3]
|
||||||
AND(32, M(&PowerPC::ppcState.spr[SPR_XER]), Imm32(0x0FFFFFFF));
|
AND(32, M(&PowerPC::ppcState.spr[SPR_XER]), Imm32(0x0FFFFFFF));
|
||||||
|
@ -467,49 +386,33 @@ void Jit64::crXXX(UGeckoInstruction inst)
|
||||||
// not required.
|
// not required.
|
||||||
|
|
||||||
// USES_CR
|
// USES_CR
|
||||||
|
// crandc or crorc or creqv or crnand or crnor
|
||||||
|
bool negateA = inst.SUBOP10 == 129 || inst.SUBOP10 == 417 || inst.SUBOP10 == 289 || inst.SUBOP10 == 225 || inst.SUBOP10 == 33;
|
||||||
|
// crnand or crnor
|
||||||
|
bool negateB = inst.SUBOP10 == 225 || inst.SUBOP10 == 33;
|
||||||
|
|
||||||
gpr.FlushLockX(ABI_PARAM1, ABI_PARAM2);
|
gpr.FlushLockX(ABI_PARAM1);
|
||||||
GetCRFieldBit(inst.CRBA >> 2, 3 - (inst.CRBA & 3), ABI_PARAM2);
|
GetCRFieldBit(inst.CRBA >> 2, 3 - (inst.CRBA & 3), ABI_PARAM1, negateA);
|
||||||
GetCRFieldBit(inst.CRBB >> 2, 3 - (inst.CRBB & 3), EAX);
|
GetCRFieldBit(inst.CRBB >> 2, 3 - (inst.CRBB & 3), EAX, negateB);
|
||||||
|
|
||||||
// Compute combined bit
|
// Compute combined bit
|
||||||
switch (inst.SUBOP10)
|
switch (inst.SUBOP10)
|
||||||
{
|
{
|
||||||
case 33: // crnor
|
case 33: // crnor: ~(A || B) == (~A && ~B)
|
||||||
OR(8, R(EAX), R(ABI_PARAM2));
|
|
||||||
NOT(8, R(EAX));
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 129: // crandc
|
case 129: // crandc
|
||||||
NOT(8, R(ABI_PARAM2));
|
case 257: // crand
|
||||||
AND(8, R(EAX), R(ABI_PARAM2));
|
AND(8, R(EAX), R(ABI_PARAM1));
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 193: // crxor
|
case 193: // crxor
|
||||||
XOR(8, R(EAX), R(ABI_PARAM2));
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 225: // crnand
|
|
||||||
AND(8, R(EAX), R(ABI_PARAM2));
|
|
||||||
NOT(8, R(EAX));
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 257: // crand
|
|
||||||
AND(8, R(EAX), R(ABI_PARAM2));
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 289: // creqv
|
case 289: // creqv
|
||||||
XOR(8, R(EAX), R(ABI_PARAM2));
|
XOR(8, R(EAX), R(ABI_PARAM1));
|
||||||
NOT(8, R(EAX));
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case 225: // crnand: ~(A && B) == (~A || ~B)
|
||||||
case 417: // crorc
|
case 417: // crorc
|
||||||
NOT(8, R(ABI_PARAM2));
|
|
||||||
OR(8, R(EAX), R(ABI_PARAM2));
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 449: // cror
|
case 449: // cror
|
||||||
OR(8, R(EAX), R(ABI_PARAM2));
|
OR(8, R(EAX), R(ABI_PARAM1));
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue