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Jit: Replace MSR/MMCR access with feature_flags access 

This has the same effect in the end, but in my opinion, doing it this
way makes it more clear for the reader why we can read from ppcState at
JIT time, something that makes no sense for everything else in ppcState.
This commit is contained in:
JosJuice 2023-08-27 12:04:18 +02:00
parent 62787085e1
commit 94b31eb4f4
7 changed files with 17 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Source/Core/Core/PowerPC/Jit64/Jit.cpp
View File

@ -445,7 +445,7 @@ bool Jit64::Cleanup()
did_something = true;
}
if (MMCR0(m_ppc_state).Hex || MMCR1(m_ppc_state).Hex)
if (m_ppc_state.feature_flags & FEATURE_FLAG_PERFMON)
{
ABI_PushRegistersAndAdjustStack({}, 0);
ABI_CallFunctionCCCP(PowerPC::UpdatePerformanceMonitor, js.downcountAmount, js.numLoadStoreInst,

6
Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
View File

@ -320,7 +320,7 @@ void Jit64::dcbx(UGeckoInstruction inst)
FixupBranch bat_lookup_failed;
MOV(32, R(effective_address), R(addr));
const u8* loop_start = GetCodePtr();
if (m_ppc_state.msr.IR)
if (m_ppc_state.feature_flags & FEATURE_FLAG_MSR_IR)
{
// Translate effective address to physical address.
bat_lookup_failed = BATAddressLookup(addr, tmp, m_jit.m_mmu.GetIBATTable().data());
@ -349,7 +349,7 @@ void Jit64::dcbx(UGeckoInstruction inst)
SwitchToFarCode();
SetJumpTarget(invalidate_needed);
if (m_ppc_state.msr.IR)
if (m_ppc_state.feature_flags & FEATURE_FLAG_MSR_IR)
SetJumpTarget(bat_lookup_failed);
BitSet32 registersInUse = CallerSavedRegistersInUse();
@ -421,7 +421,7 @@ void Jit64::dcbz(UGeckoInstruction inst)
end_dcbz_hack = J_CC(CC_L);
}
bool emit_fast_path = m_ppc_state.msr.DR && m_jit.jo.fastmem_arena;
bool emit_fast_path = (m_ppc_state.feature_flags & FEATURE_FLAG_MSR_DR) && m_jit.jo.fastmem_arena;
if (emit_fast_path)
{

4
Source/Core/Core/PowerPC/Jit64/Jit_LoadStorePaired.cpp
View File

@ -23,7 +23,7 @@ void Jit64::psq_stXX(UGeckoInstruction inst)
JITDISABLE(bJITLoadStorePairedOff);
// For performance, the AsmCommon routines assume address translation is on.
FALLBACK_IF(!m_ppc_state.msr.DR);
FALLBACK_IF(!(m_ppc_state.feature_flags & FEATURE_FLAG_MSR_DR));
s32 offset = inst.SIMM_12;
bool indexed = inst.OPCD == 4;
@ -112,7 +112,7 @@ void Jit64::psq_lXX(UGeckoInstruction inst)
JITDISABLE(bJITLoadStorePairedOff);
// For performance, the AsmCommon routines assume address translation is on.
FALLBACK_IF(!m_ppc_state.msr.DR);
FALLBACK_IF(!(m_ppc_state.feature_flags & FEATURE_FLAG_MSR_DR));
s32 offset = inst.SIMM_12;
bool indexed = inst.OPCD == 4;

6
Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp
View File

@ -371,7 +371,8 @@ void EmuCodeBlock::SafeLoadToReg(X64Reg reg_value, const Gen::OpArg& opAddress,
}
FixupBranch exit;
const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || m_jit.m_ppc_state.msr.DR;
const bool dr_set =
(flags & SAFE_LOADSTORE_DR_ON) || (m_jit.m_ppc_state.feature_flags & FEATURE_FLAG_MSR_DR);
const bool fast_check_address =
!force_slow_access && dr_set && m_jit.jo.fastmem_arena && !m_jit.m_ppc_state.m_enable_dcache;
if (fast_check_address)
@ -544,7 +545,8 @@ void EmuCodeBlock::SafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int acces
}
FixupBranch exit;
const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || m_jit.m_ppc_state.msr.DR;
const bool dr_set =
(flags & SAFE_LOADSTORE_DR_ON) || (m_jit.m_ppc_state.feature_flags & FEATURE_FLAG_MSR_DR);
const bool fast_check_address =
!force_slow_access && dr_set && m_jit.jo.fastmem_arena && !m_jit.m_ppc_state.m_enable_dcache;
if (fast_check_address)

2
Source/Core/Core/PowerPC/JitArm64/Jit.cpp
View File

@ -276,7 +276,7 @@ void JitArm64::Cleanup()
SetJumpTarget(exit);
}
if (MMCR0(m_ppc_state).Hex || MMCR1(m_ppc_state).Hex)
if (m_ppc_state.feature_flags & FEATURE_FLAG_PERFMON)
{
ABI_CallFunction(&PowerPC::UpdatePerformanceMonitor, js.downcountAmount, js.numLoadStoreInst,
js.numFloatingPointInst, &m_ppc_state);

4
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
View File

@ -727,7 +727,7 @@ void JitArm64::dcbx(UGeckoInstruction inst)
// Translate effective address to physical address.
const u8* loop_start = GetCodePtr();
FixupBranch bat_lookup_failed;
if (m_ppc_state.msr.IR)
if (m_ppc_state.feature_flags & FEATURE_FLAG_MSR_IR)
{
bat_lookup_failed =
BATAddressLookup(physical_addr, effective_addr, WA, m_mmu.GetIBATTable().data());
@ -756,7 +756,7 @@ void JitArm64::dcbx(UGeckoInstruction inst)
SwitchToFarCode();
SetJumpTarget(invalidate_needed);
if (m_ppc_state.msr.IR)
if (m_ppc_state.feature_flags & FEATURE_FLAG_MSR_IR)
SetJumpTarget(bat_lookup_failed);
BitSet32 gprs_to_push = gpr.GetCallerSavedUsed();

6
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
View File

@ -23,7 +23,8 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
JITDISABLE(bJITLoadStorePairedOff);
// If fastmem is enabled, the asm routines assume address translation is on.
FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem && !m_ppc_state.msr.DR);
FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem &&
!(m_ppc_state.feature_flags & FEATURE_FLAG_MSR_DR));
// X30 is LR
// X0 is the address
@ -153,7 +154,8 @@ void JitArm64::psq_stXX(UGeckoInstruction inst)
JITDISABLE(bJITLoadStorePairedOff);
// If fastmem is enabled, the asm routines assume address translation is on.
FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem && !m_ppc_state.msr.DR);
FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem &&
!(m_ppc_state.feature_flags & FEATURE_FLAG_MSR_DR));
// X30 is LR
// X0 contains the scale