Added OPTYPE_LOADPS and OPTYPE_STOREPS instruction types to the PPC table.

Updated ARAM DMA and FIFO write exception checking to uses these types.

Conflicts:
	Source/Core/Core/PowerPC/Interpreter/Interpreter_Tables.cpp
	Source/Core/Core/PowerPC/PPCTables.h
This commit is contained in:
skidau 2014-09-07 15:46:29 +10:00
parent 0f256715e0
commit 945d431171
4 changed files with 11 additions and 7 deletions

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@ -448,7 +448,7 @@ static void UpdateInterrupts()
if (jit && PC != 0 && (jit->js.dspARAMAddresses.find(PC)) == (jit->js.dspARAMAddresses.end()) && (g_dspState.DSPControl.ARAM & g_dspState.DSPControl.ARAM_mask))
{
int type = GetOpInfo(Memory::ReadUnchecked_U32(PC))->type;
if (type == OPTYPE_STORE || type == OPTYPE_STOREFP || (type == OPTYPE_PS && GetOpInfo(Memory::ReadUnchecked_U32(PC))->opname == "psq_st"))
if (type == OPTYPE_STORE || type == OPTYPE_STOREFP || (type == OPTYPE_STOREPS))
{
jit->js.dspARAMAddresses.insert(PC);
@ -534,7 +534,8 @@ static void Do_ARAM_DMA()
g_dspState.DSPControl.DMAState = 1;
CoreTiming::ScheduleEvent_Threadsafe(0, et_CompleteARAM);
// Force an early exception check on large transfers. Fixes RE2 audio.
// Force an early exception check on large transfers (transfers longer than 250+ ticks).
// The shorter transfers are checked by dspARAMAddresses. Fixes RE2 audio.
CoreTiming::ForceExceptionCheck(250);
// Real hardware DMAs in 32byte chunks, but we can get by with 8byte chunks

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@ -90,7 +90,7 @@ void STACKALIGN CheckGatherPipe()
{
// Log only stores, fp stores and ps stores, filtering out other instructions arrived via optimizeGatherPipe
int type = GetOpInfo(Memory::ReadUnchecked_U32(PC))->type;
if (type == OPTYPE_STORE || type == OPTYPE_STOREFP || (type == OPTYPE_PS && !strcmp(GetOpInfo(Memory::ReadUnchecked_U32(PC))->opname, "psq_st")))
if (type == OPTYPE_STORE || type == OPTYPE_STOREFP || type == OPTYPE_STOREPS)
{
jit->js.fifoWriteAddresses.insert(PC);

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@ -79,10 +79,10 @@ static GekkoOPTemplate primarytable[] =
{54, Interpreter::stfd, {"stfd", OPTYPE_STOREFP, FL_IN_FLOAT_S | FL_IN_A | FL_USE_FPU | FL_LOADSTORE, 1, 0, 0, 0}},
{55, Interpreter::stfdu, {"stfdu", OPTYPE_STOREFP, FL_IN_FLOAT_S | FL_OUT_A | FL_IN_A | FL_USE_FPU | FL_LOADSTORE, 1, 0, 0, 0}},
{56, Interpreter::psq_l, {"psq_l", OPTYPE_PS, FL_OUT_FLOAT_S | FL_IN_A | FL_USE_FPU | FL_LOADSTORE, 1, 0, 0, 0}},
{57, Interpreter::psq_lu, {"psq_lu", OPTYPE_PS, FL_OUT_FLOAT_S | FL_OUT_A | FL_IN_A | FL_USE_FPU | FL_LOADSTORE, 1, 0, 0, 0}},
{60, Interpreter::psq_st, {"psq_st", OPTYPE_PS, FL_IN_FLOAT_S | FL_IN_A | FL_USE_FPU | FL_LOADSTORE, 1, 0, 0, 0}},
{61, Interpreter::psq_stu, {"psq_stu", OPTYPE_PS, FL_IN_FLOAT_S | FL_OUT_A | FL_IN_A | FL_USE_FPU | FL_LOADSTORE, 1, 0, 0, 0}},
{56, Interpreter::psq_l, {"psq_l", OPTYPE_LOADPS, FL_OUT_FLOAT_S | FL_IN_A | FL_USE_FPU | FL_LOADSTORE, 1, 0, 0, 0}},
{57, Interpreter::psq_lu, {"psq_lu", OPTYPE_LOADPS, FL_OUT_FLOAT_S | FL_OUT_A | FL_IN_A | FL_USE_FPU | FL_LOADSTORE, 1, 0, 0, 0}},
{60, Interpreter::psq_st, {"psq_st", OPTYPE_STOREPS, FL_IN_FLOAT_S | FL_IN_A | FL_USE_FPU | FL_LOADSTORE, 1, 0, 0, 0}},
{61, Interpreter::psq_stu, {"psq_stu", OPTYPE_STOREPS, FL_IN_FLOAT_S | FL_OUT_A | FL_IN_A | FL_USE_FPU | FL_LOADSTORE, 1, 0, 0, 0}},
//missing: 0, 5, 6, 9, 22, 30, 62, 58
{0, Interpreter::unknown_instruction, {"unknown_instruction", OPTYPE_UNKNOWN, 0, 0, 0, 0, 0}},

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@ -70,6 +70,9 @@ enum
OPTYPE_STOREFP ,
OPTYPE_DOUBLEFP,
OPTYPE_SINGLEFP,
OPTYPE_LOADPS ,
OPTYPE_STOREPS ,
OPTYPE_FPU ,
OPTYPE_PS ,
OPTYPE_DCACHE ,
OPTYPE_ICACHE ,