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DSP: fixed compiler warnings and 2 crash bugs 

made the dsp_code test use our lable table rather than the table which was there before (and had few mistakes).
The other tests need to be fixed as well.



git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3063 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee 2009-04-24 14:36:31 +00:00
parent 9e427a4e59
commit 92e6d7c283
3 changed files with 206 additions and 268 deletions
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51
Source/Core/DSPCore/Src/assemble.cpp
View File

@ -77,10 +77,10 @@ static const char *err_string[] =
"Number out of range" "Number out of range"
}; };
DSPAssembler::DSPAssembler(const AssemblerSettings &settings) DSPAssembler::DSPAssembler(const AssemblerSettings &settings) :
: current_param(0), m_cur_addr(0),
cur_addr(0), m_cur_pass(0),
cur_pass(0), m_current_param(0),
settings_(settings) settings_(settings)
{ {
gdg_buffer = NULL; gdg_buffer = NULL;
@ -128,11 +128,11 @@ void DSPAssembler::ShowError(err_t err_code, const char *extra_info)
else else
buf_ptr += sprintf(buf_ptr, "ERROR: %s : %s\n", err_string[err_code], extra_info); buf_ptr += sprintf(buf_ptr, "ERROR: %s : %s\n", err_string[err_code], extra_info);
if (current_param == 0) if (m_current_param == 0)
buf_ptr += sprintf(buf_ptr, "ERROR: %s Line: %d : %s\n", err_string[err_code], code_line, extra_info); buf_ptr += sprintf(buf_ptr, "ERROR: %s Line: %d : %s\n", err_string[err_code], code_line, extra_info);
else else
buf_ptr += sprintf(buf_ptr, "ERROR: %s Line: %d Param: %d : %s\n", buf_ptr += sprintf(buf_ptr, "ERROR: %s Line: %d Param: %d : %s\n",
err_string[err_code], code_line, current_param, extra_info); err_string[err_code], code_line, m_current_param, extra_info);
last_error_str = error_buffer; last_error_str = error_buffer;
last_error = err_code; last_error = err_code;
} }
@ -236,7 +236,7 @@ s32 DSPAssembler::ParseValue(const char *str)
u16 value; u16 value;
if (labels.GetLabelValue(ptr, &value)) if (labels.GetLabelValue(ptr, &value))
return value; return value;
if (cur_pass == 2) if (m_cur_pass == 2)
ShowError(ERR_UNKNOWN_LABEL, str); ShowError(ERR_UNKNOWN_LABEL, str);
} }
} }
@ -532,7 +532,7 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
if (ext) fprintf(stderr, "(ext) "); if (ext) fprintf(stderr, "(ext) ");
if (par[i].val >= 0x1e && par[i].val <= 0x1f) { if (par[i].val >= 0x1e && par[i].val <= 0x1f) {
fprintf(stderr, "%i : %s", code_line, cur_line.c_str()); fprintf(stderr, "%i : %s", code_line, cur_line.c_str());
fprintf(stderr, "WARNING: $ACM%d register used instead of $ACC%d register Line: %d Param: %d\n", fprintf(stderr, "WARNING: $ACM%d register used instead of $ACC%d register Line: %d Param: %d Ext: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param, ext); (par[i].val & 1), (par[i].val & 1), code_line, current_param, ext);
} }
else if (par[i].val >= 0x1c && par[i].val <= 0x1d) { else if (par[i].val >= 0x1c && par[i].val <= 0x1d) {
@ -683,7 +683,7 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
continue; continue;
} }
} }
current_param = 0; m_current_param = 0;
return true; return true;
} }
@ -691,20 +691,20 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
// Merge opcode with params. // Merge opcode with params.
void DSPAssembler::BuildCode(const opc_t *opc, param_t *par, u32 par_count, u16 *outbuf) void DSPAssembler::BuildCode(const opc_t *opc, param_t *par, u32 par_count, u16 *outbuf)
{ {
outbuf[cur_addr] |= opc->opcode; outbuf[m_cur_addr] |= opc->opcode;
for (u32 i = 0; i < par_count; i++) for (u32 i = 0; i < par_count; i++)
{ {
// Ignore the "reverse" parameters since they are implicit. // Ignore the "reverse" parameters since they are implicit.
if (opc->params[i].type != P_ACC_D && opc->params[i].type != P_ACCM_D) if (opc->params[i].type != P_ACC_D && opc->params[i].type != P_ACCM_D)
{ {
u16 t16 = outbuf[cur_addr + opc->params[i].loc]; u16 t16 = outbuf[m_cur_addr + opc->params[i].loc];
u16 v16 = par[i].val; u16 v16 = par[i].val;
if (opc->params[i].lshift > 0) if (opc->params[i].lshift > 0)
v16 <<= opc->params[i].lshift; v16 <<= opc->params[i].lshift;
else else
v16 >>= -opc->params[i].lshift; v16 >>= -opc->params[i].lshift;
v16 &= opc->params[i].mask; v16 &= opc->params[i].mask;
outbuf[cur_addr + opc->params[i].loc] = t16 | v16; outbuf[m_cur_addr + opc->params[i].loc] = t16 | v16;
} }
} }
} }
@ -722,7 +722,7 @@ void DSPAssembler::InitPass(int pass)
aliases["S16"] = "SET16"; aliases["S16"] = "SET16";
aliases["S40"] = "SET40"; aliases["S40"] = "SET40";
} }
cur_addr = 0; m_cur_addr = 0;
cur_segment = SEGMENT_CODE; cur_segment = SEGMENT_CODE;
segment_addr[SEGMENT_CODE] = 0; segment_addr[SEGMENT_CODE] = 0;
segment_addr[SEGMENT_DATA] = 0; segment_addr[SEGMENT_DATA] = 0;
@ -744,11 +744,11 @@ bool DSPAssembler::AssembleFile(const char *fname, int pass)
printf("Pass %d\n", pass); printf("Pass %d\n", pass);
code_line = 0; code_line = 0;
cur_pass = pass; m_cur_pass = pass;
#define LINEBUF_SIZE 1024 #define LINEBUF_SIZE 1024
char linebuffer[LINEBUF_SIZE]; char linebuffer[LINEBUF_SIZE];
while (!feof(fsrc) && !failed) while (!failed && !feof(fsrc))
{ {
int opcode_size = 0; int opcode_size = 0;
memset(linebuffer, 0, LINEBUF_SIZE); memset(linebuffer, 0, LINEBUF_SIZE);
@ -758,8 +758,8 @@ bool DSPAssembler::AssembleFile(const char *fname, int pass)
//printf("A: %s", linebuffer); //printf("A: %s", linebuffer);
code_line++; code_line++;
param_t params[10] = {0}; param_t params[10] = {{0}};
param_t params_ext[10] = {0}; param_t params_ext[10] = {{0}};
for (int i = 0; i < LINEBUF_SIZE; i++) for (int i = 0; i < LINEBUF_SIZE; i++)
{ {
@ -870,7 +870,7 @@ bool DSPAssembler::AssembleFile(const char *fname, int pass)
if (label) if (label)
{ {
// there is a valid label so lets store it in labels table // there is a valid label so lets store it in labels table
u32 lval = cur_addr; u32 lval = m_cur_addr;
if (opcode) if (opcode)
{ {
if (strcmp(opcode, "EQU") == 0) if (strcmp(opcode, "EQU") == 0)
@ -922,7 +922,7 @@ bool DSPAssembler::AssembleFile(const char *fname, int pass)
if (strcmp("ORG", opcode) == 0) if (strcmp("ORG", opcode) == 0)
{ {
if (params[0].type == P_VAL) if (params[0].type == P_VAL)
cur_addr = params[0].val; m_cur_addr = params[0].val;
else else
ShowError(ERR_EXPECTED_PARAM_VAL); ShowError(ERR_EXPECTED_PARAM_VAL);
continue; continue;
@ -932,12 +932,12 @@ bool DSPAssembler::AssembleFile(const char *fname, int pass)
{ {
if (params[0].type == P_STR) if (params[0].type == P_STR)
{ {
segment_addr[cur_segment] = cur_addr; segment_addr[cur_segment] = m_cur_addr;
if (strcmp("DATA", params[0].str) == 0) if (strcmp("DATA", params[0].str) == 0)
cur_segment = SEGMENT_DATA; cur_segment = SEGMENT_DATA;
if (strcmp("CODE", params[0].str) == 0) if (strcmp("CODE", params[0].str) == 0)
cur_segment = SEGMENT_CODE; cur_segment = SEGMENT_CODE;
cur_addr = segment_addr[cur_segment]; m_cur_addr = segment_addr[cur_segment];
} }
else else
ShowError(ERR_EXPECTED_PARAM_STR); ShowError(ERR_EXPECTED_PARAM_STR);
@ -975,20 +975,21 @@ bool DSPAssembler::AssembleFile(const char *fname, int pass)
if (pass == 2) if (pass == 2)
{ {
// generate binary // generate binary
((u16 *)gdg_buffer)[cur_addr] = 0x0000; ((u16 *)gdg_buffer)[m_cur_addr] = 0x0000;
BuildCode(opc, params, params_count, (u16 *)gdg_buffer); BuildCode(opc, params, params_count, (u16 *)gdg_buffer);
if (opc_ext) if (opc_ext)
BuildCode(opc_ext, params_ext, params_count_ext, (u16 *)gdg_buffer); BuildCode(opc_ext, params_ext, params_count_ext, (u16 *)gdg_buffer);
} }
cur_addr += opcode_size; m_cur_addr += opcode_size;
}; };
if (gdg_buffer == NULL) if (gdg_buffer == NULL)
{ {
gdg_buffer_size = cur_addr; gdg_buffer_size = m_cur_addr;
gdg_buffer = (char *)malloc(gdg_buffer_size * sizeof(u16) + 4); gdg_buffer = (char *)malloc(gdg_buffer_size * sizeof(u16) + 4);
memset(gdg_buffer, 0, gdg_buffer_size * sizeof(u16)); memset(gdg_buffer, 0, gdg_buffer_size * sizeof(u16));
} }
fclose(fsrc); if (! failed)
fclose(fsrc);
return !failed; return !failed;
} }

8
Source/Core/DSPCore/Src/assemble.h
View File

@ -117,8 +117,8 @@ private:
std::string include_dir; std::string include_dir;
std::string cur_line; std::string cur_line;
u32 cur_addr; u32 m_cur_addr;
u8 cur_pass; u8 m_cur_pass;
LabelMap labels; LabelMap labels;
@ -133,8 +133,8 @@ private:
segment_t cur_segment; segment_t cur_segment;
u32 segment_addr[SEGMENT_MAX]; u32 segment_addr[SEGMENT_MAX];
int current_param; int m_current_param;
const AssemblerSettings settings_; const AssemblerSettings settings_;
}; };
#endif // _DSP_ASSEMBLE_H #endif // _DSP_ASSEMBLE_H

415
Source/DSPSpy/tests/dsp_code.ds
View File

@ -1,72 +1,9 @@
; This is the trojan program we send to the DSP from DSPSpy to figure it out. ; This is the trojan program we send to the DSP from DSPSpy to figure it out.
REGS_BASE: equ 0x0f80
MEM_HI: equ 0x0f7E
MEM_LO: equ 0x0f7F
; A lot of constant definitions. ;
DSCR: equ 0xffc9 ; DSP DMA Control Reg
DSBL: equ 0xffcb ; DSP DMA Block Length
DSPA: equ 0xffcd ; DSP DMA DMEM Address
DSMAH: equ 0xffce ; DSP DMA Mem Address H
DSMAL: equ 0xffcf ; DSP DMA Mem Address L
ACSAH: equ 0xffd4
ACSAL: equ 0xffd5
ACEAH: equ 0xffd6
ACEAL: equ 0xffd7
ACCAH: equ 0xffd8
ACCAL: equ 0xffd9
AMDM: equ 0xffef ; ARAM DMA Request Mask
DIRQ: equ 0xfffb ; DSP Irq Request
DMBH: equ 0xfffc ; DSP Mailbox H
DMBL: equ 0xfffd ; DSP Mailbox L
CMBH: equ 0xfffe ; CPU Mailbox H
CMBL: equ 0xffff ; CPU Mailbox L
R00: equ 0x00
R01: equ 0x01
R02: equ 0x02
R03: equ 0x03
R04: equ 0x04
R05: equ 0x05
R06: equ 0x06
R07: equ 0x07
R08: equ 0x08
R09: equ 0x09
R0A: equ 0x0a
R0B: equ 0x0b
R0C: equ 0x0c
R0D: equ 0x0d
R0E: equ 0x0e
R0F: equ 0x0f
R10: equ 0x10
R11: equ 0x11
R12: equ 0x12
R13: equ 0x13
R14: equ 0x14
R15: equ 0x15
R16: equ 0x16
R17: equ 0x17
R18: equ 0x18
R19: equ 0x19
R1A: equ 0x1a
R1B: equ 0x1b
R1C: equ 0x1c
R1D: equ 0x1d
R1E: equ 0x1e
R1F: equ 0x1f
ACH0: equ 0x10
ACH1: equ 0x11
ACL0: equ 0x1e
ACL1: equ 0x1f
DSP_CR_IMEM: equ 2
DSP_CR_TO_CPU: equ 1
REGS_BASE: equ 0x0f80
MEM_HI: equ 0x0f7E
MEM_LO: equ 0x0f7F
; CODE STARTS HERE. ; CODE STARTS HERE.
; Interrupt vectors 8 vectors, 2 opcodes each ; Interrupt vectors 8 vectors, 2 opcodes each
@ -104,17 +41,17 @@ main:
si @DIRQ, #0x0001 si @DIRQ, #0x0001
call wait_for_cpu_mbox call wait_for_cpu_mbox
lrs $ACL0, @CMBL lrs $AC0.M, @CMBL
andi $acl1, #0x7fff andi $ac1.m, #0x7fff
sr @MEM_HI, $ACL1 sr @MEM_HI, $AC1.M
sr @MEM_LO, $ACL0 sr @MEM_LO, $AC0.M
lri $r18, #0 lri $ax0.l, #0
lri $r19, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU) lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
lri $r1a, #0x2000 lri $ax0.h, #0x2000
lr $r1c, @MEM_HI lr $ac0.l, @MEM_HI
lr $r1e, @MEM_LO lr $ac0.m, @MEM_LO
call do_dma call do_dma
@ -126,54 +63,54 @@ main:
si @DIRQ, #0x0001 si @DIRQ, #0x0001
call wait_for_cpu_mbox call wait_for_cpu_mbox
lrs $ACL0, @CMBL lrs $AC0.M, @CMBL
andi $acl1, #0x7fff andi $ac1.m, #0x7fff
sr @MEM_HI, $ACL1 sr @MEM_HI, $AC1.M
sr @MEM_LO, $ACL0 sr @MEM_LO, $AC0.M
lri $r18, #REGS_BASE lri $ax0.l, #REGS_BASE
lri $r19, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU) lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
lri $r1a, #0x80 lri $ax0.h, #0x80
lr $r1c, @MEM_HI lr $ac0.l, @MEM_HI
lr $r1e, @MEM_LO lr $ac0.m, @MEM_LO
call do_dma call do_dma
; Read in all the registers from RAM ; Read in all the registers from RAM
lri $r00, #REGS_BASE+1 lri $ar0, #REGS_BASE+1
lrri $r01, @$r00 lrri $ar1, @$ar0
lrri $r02, @$r00 lrri $ar2, @$ar0
lrri $r03, @$r00 lrri $ar3, @$ar0
lrri $r04, @$r00 lrri $ix0, @$ar0
lrri $r05, @$r00 lrri $ix1, @$ar0
lrri $r06, @$r00 lrri $ix2, @$ar0
lrri $r07, @$r00 lrri $ix3, @$ar0
lrri $r08, @$r00 lrri $r08, @$ar0
lrri $r09, @$r00 lrri $r09, @$ar0
lrri $r0a, @$r00 lrri $r10, @$ar0
lrri $r0b, @$r00 lrri $r11, @$ar0
lrri $r0c, @$r00 lrri $st0, @$ar0
lrri $r0d, @$r00 lrri $st1, @$ar0
lrri $r0e, @$r00 lrri $st2, @$ar0
lrri $r0f, @$r00 lrri $st3, @$ar0
lrri $r10, @$r00 lrri $ac0.h, @$ar0
lrri $r11, @$r00 lrri $ac1.h, @$ar0
lrri $r12, @$r00 lrri $cr, @$ar0
lrri $r13, @$r00 lrri $sr, @$ar0
lrri $r14, @$r00 lrri $prod.l, @$ar0
lrri $r15, @$r00 lrri $prod.m1, @$ar0
lrri $r16, @$r00 lrri $prod.h, @$ar0
lrri $r17, @$r00 lrri $prod.m2, @$ar0
lrri $r18, @$r00 lrri $ax0.l, @$ar0
lrri $r19, @$r00 lrri $ax1.l, @$ar0
lrri $r1a, @$r00 lrri $ax0.h, @$ar0
lrri $r1b, @$r00 lrri $ax1.h, @$ar0
lrri $r1c, @$r00 lrri $ac0.l, @$ar0
lrri $r1d, @$r00 lrri $ac1.l, @$ar0
lrri $r1e, @$r00 lrri $ac0.m, @$ar0
lrri $r1f, @$r00 lrri $ac1.m, @$ar0
lr $r00, @REGS_BASE lr $ar0, @REGS_BASE
; Right here we are at a specific predetermined state. ; Right here we are at a specific predetermined state.
; Ideal environment to try instructions. ; Ideal environment to try instructions.
@ -189,7 +126,7 @@ main:
lris $AC1.M, #0xcc lris $AC1.M, #0xcc
nop nop
mrr $r00, $r13 mrr $ar0, $sr
call send_back call send_back
set40 set40
@ -198,7 +135,7 @@ main:
lris $AC1.M, #0xcc lris $AC1.M, #0xcc
nop nop
nop nop
mrr $r00, $r13 mrr $ar0, $sr
call send_back call send_back
cw 0xa100 cw 0xa100
@ -454,60 +391,60 @@ dead_loop:
jmp dead_loop jmp dead_loop
; Utility function to do DMA. ; Utility function to do DMA.
; r1c:r1e - external address. ; ac0.l:ac0.m - external address.
; r18 - address in DSP ; ax0.l - address in DSP
do_dma: do_dma:
sr @DSMAH, $r1c sr @DSMAH, $ac0.l
sr @DSMAL, $r1e sr @DSMAL, $ac0.m
sr @DSPA, $r18 sr @DSPA, $ax0.l
sr @DSCR, $r19 sr @DSCR, $ax1.l
sr @DSBL, $r1a ; This kicks off the DMA. sr @DSBL, $ax0.h ; This kicks off the DMA.
; Waits for said DMA to complete by watching a bit in DSCR. ; Waits for said DMA to complete by watching a bit in DSCR.
wait_dma: wait_dma:
LRS $ACL1, @DSCR LRS $AC1.M, @DSCR
andcf $acl1, #0x0004 andcf $ac1.m, #0x0004
JLZ wait_dma JLZ wait_dma
RET RET
; This waits for a mail to arrive in the DSP in-mailbox. ; This waits for a mail to arrive in the DSP in-mailbox.
wait_for_dsp_mbox: wait_for_dsp_mbox:
lrs $ACL1, @DMBH lrs $AC1.M, @DMBH
andcf $acl1, #0x8000 andcf $ac1.m, #0x8000
jlz wait_for_dsp_mbox jlz wait_for_dsp_mbox
ret ret
; This waits for the CPU to grab a mail that we just sent from the DSP. ; This waits for the CPU to grab a mail that we just sent from the DSP.
wait_for_cpu_mbox: wait_for_cpu_mbox:
lrs $ACL1, @cmbh lrs $AC1.M, @cmbh
andcf $acl1, #0x8000 andcf $ac1.m, #0x8000
jlnz wait_for_cpu_mbox jlnz wait_for_cpu_mbox
ret ret
; IRQ handlers. Not entirely sure what good they do currently. ; IRQ handlers. Not entirely sure what good they do currently.
irq0: irq0:
lri $acl0, #0x0000 lri $ac0.m, #0x0000
jmp irq jmp irq
irq1: irq1:
lri $acl0, #0x0001 lri $ac0.m, #0x0001
jmp irq jmp irq
irq2: irq2:
lri $acl0, #0x0002 lri $ac0.m, #0x0002
jmp irq jmp irq
irq3: irq3:
lri $acl0, #0x0003 lri $ac0.m, #0x0003
jmp irq jmp irq
irq4: irq4:
lri $acl0, #0x0004 lri $ac0.m, #0x0004
jmp irq jmp irq
irq5: irq5:
; No idea what this code is doing. ; No idea what this code is doing.
set16 set16
mrr $r0d, $r1c mrr $st1, $ac0.l
mrr $r0d, $r1e mrr $st1, $ac0.m
clr $acc0 clr $acc0
mrr $r1e, $r0d mrr $ac0.m, $st1
mrr $r1c, $r0d mrr $ac0.l, $st1
nop ; Or why there's a nop sled here. nop ; Or why there's a nop sled here.
nop nop
nop nop
@ -516,22 +453,22 @@ irq5:
nop nop
rti rti
lri $acl0, #0x0005 lri $ac0.m, #0x0005
jmp irq jmp irq
irq6: irq6:
lri $acl0, #0x0006 lri $ac0.m, #0x0006
jmp irq jmp irq
irq7: irq7:
lri $acl0, #0x0007 lri $ac0.m, #0x0007
jmp irq jmp irq
irq: irq:
lrs $ACL1, @DMBH lrs $AC1.M, @DMBH
andcf $acl1, #0x8000 andcf $ac1.m, #0x8000
jlz irq jlz irq
si @DMBH, #0x8BAD si @DMBH, #0x8BAD
sr @DMBL, $r0b sr @DMBL, $r11
;sr @DMBL, $acl0 ;sr @DMBL, $ac0.m
si @DIRQ, #0x0001 si @DIRQ, #0x0001
halt halt
@ -541,56 +478,56 @@ send_back:
; make state safe. ; make state safe.
set16 set16
; store registers to reg table ; store registers to reg table
sr @REGS_BASE, $r00 sr @REGS_BASE, $ar0
lri $r00, #(REGS_BASE + 1) lri $ar0, #(REGS_BASE + 1)
srri @$r00, $r01 srri @$ar0, $ar1
srri @$r00, $r02 srri @$ar0, $ar2
srri @$r00, $r03 srri @$ar0, $ar3
srri @$r00, $r04 srri @$ar0, $ix0
srri @$r00, $r05 srri @$ar0, $ix1
srri @$r00, $r06 srri @$ar0, $ix2
srri @$r00, $r07 srri @$ar0, $ix3
srri @$r00, $r08 srri @$ar0, $r08
srri @$r00, $r09 srri @$ar0, $r09
srri @$r00, $r0a srri @$ar0, $r10
srri @$r00, $r0b srri @$ar0, $r11
srri @$r00, $r0c srri @$ar0, $st0
srri @$r00, $r0d srri @$ar0, $st1
srri @$r00, $r0e srri @$ar0, $st2
srri @$r00, $r0f srri @$ar0, $st3
srri @$r00, $r10 srri @$ar0, $ac0.h
srri @$r00, $r11 srri @$ar0, $ac1.h
srri @$r00, $r12 srri @$ar0, $cr
srri @$r00, $r13 srri @$ar0, $sr
srri @$r00, $r14 srri @$ar0, $prod.l
srri @$r00, $r15 srri @$ar0, $prod.m1
srri @$r00, $r16 srri @$ar0, $prod.h
srri @$r00, $r17 srri @$ar0, $prod.m2
srri @$r00, $r18 srri @$ar0, $ax0.l
srri @$r00, $r19 srri @$ar0, $ax1.l
srri @$r00, $r1a srri @$ar0, $ax0.h
srri @$r00, $r1b srri @$ar0, $ax1.h
srri @$r00, $r1c srri @$ar0, $ac0.l
srri @$r00, $r1d srri @$ar0, $ac1.l
srri @$r00, $r1e srri @$ar0, $ac0.m
srri @$r00, $r1f srri @$ar0, $ac1.m
; Regs are stored. Prepare DMA. ; Regs are stored. Prepare DMA.
lri $r18, #0x0000 lri $ax0.l, #0x0000
lri $r19, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU) lri $ax1.l, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
lri $r1a, #0x200 lri $ax0.h, #0x200
lr $r1c, @MEM_HI lr $ac0.l, @MEM_HI
lr $r1e, @MEM_LO lr $ac0.m, @MEM_LO
lri $r01, #8+8 lri $ar1, #8+8
; Now, why are we looping here? ; Now, why are we looping here?
bloop $r01, dma_copy bloop $ar1, dma_copy
call do_dma call do_dma
addi $r1e, #0x200 addi $ac0.m, #0x200
mrr $r1f, $r18 mrr $ac1.m, $ax0.l
addi $r1f, #0x100 addi $ac1.m, #0x100
mrr $r18, $r1f mrr $ax0.l, $ac1.m
nop nop
dma_copy: dma_copy:
@ -604,43 +541,43 @@ dma_copy:
; wait for the CPU to recieve our response before we execute the next op ; wait for the CPU to recieve our response before we execute the next op
call wait_for_cpu_mbox call wait_for_cpu_mbox
lrs $ACL0, @CMBL lrs $AC0.M, @CMBL
andi $acl1, #0x7fff andi $ac1.m, #0x7fff
; Restore all regs again so we're ready to execute another op. ; Restore all regs again so we're ready to execute another op.
lri $r00, #REGS_BASE+1 lri $ar0, #REGS_BASE+1
lrri $r01, @$r00 lrri $ar1, @$ar0
lrri $r02, @$r00 lrri $ar2, @$ar0
lrri $r03, @$r00 lrri $ar3, @$ar0
lrri $r04, @$r00 lrri $ix0, @$ar0
lrri $r05, @$r00 lrri $ix1, @$ar0
lrri $r06, @$r00 lrri $ix2, @$ar0
lrri $r07, @$r00 lrri $ix3, @$ar0
lrri $r08, @$r00 lrri $r08, @$ar0
lrri $r09, @$r00 lrri $r09, @$ar0
lrri $r0a, @$r00 lrri $r10, @$ar0
lrri $r0b, @$r00 lrri $r11, @$ar0
lrri $r0c, @$r00 lrri $st0, @$ar0
lrri $r0d, @$r00 lrri $st1, @$ar0
lrri $r0e, @$r00 lrri $st2, @$ar0
lrri $r0f, @$r00 lrri $st3, @$ar0
lrri $r10, @$r00 lrri $ac0.h, @$ar0
lrri $r11, @$r00 lrri $ac1.h, @$ar0
lrri $r12, @$r00 lrri $cr, @$ar0
lrri $r13, @$r00 lrri $sr, @$ar0
lrri $r14, @$r00 lrri $prod.l, @$ar0
lrri $r15, @$r00 lrri $prod.m1, @$ar0
lrri $r16, @$r00 lrri $prod.h, @$ar0
lrri $r17, @$r00 lrri $prod.m2, @$ar0
lrri $r18, @$r00 lrri $ax0.l, @$ar0
lrri $r19, @$r00 lrri $ax1.l, @$ar0
lrri $r1a, @$r00 lrri $ax0.h, @$ar0
lrri $r1b, @$r00 lrri $ax1.h, @$ar0
lrri $r1c, @$r00 lrri $ac0.l, @$ar0
lrri $r1d, @$r00 lrri $ac1.l, @$ar0
lrri $r1e, @$r00 lrri $ac0.m, @$ar0
lrri $r1f, @$r00 lrri $ac1.m, @$ar0
lr $r00, @REGS_BASE lr $ar0, @REGS_BASE
ret ; from send_back ret ; from send_back
@ -652,23 +589,23 @@ send_back_40:
set40 set40
ret ret
; This one's odd. Doesn't look like it should work since it uses acl0 but ; This one's odd. Doesn't look like it should work since it uses ac0.m but
; increments acm0... (acc0) ; increments acm0... (acc0)
dump_memory: dump_memory:
lri $r02, #0x0000 lri $ar2, #0x0000
lri $acl0, #0x1000 lri $ac0.m, #0x1000
lri $r01, #0x1000 lri $ar1, #0x1000
bloop $r01, _fill_loop2 bloop $ar1, _fill_loop2
mrr $r03, $acl0 mrr $ar3, $ac0.m
nx'ld : $AX0.H, $AX1.H, @$AR0 nx'ld : $AX0.H, $AX1.H, @$AR0
mrr $r1f, $r00 mrr $ac1.m, $ar0
mrr $r00, $r02 mrr $ar0, $ar2
srri @$r00, $r1b srri @$ar0, $ax1.h
mrr $r02, $r00 mrr $ar2, $ar0
mrr $r00, $r1f mrr $ar0, $ac1.m
addis $acc0, #0x1 addis $acc0, #0x1