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Merge pull request #9872 from JosJuice/jitarm64-msr-ee 

JitArm64: Check MSR.EE for external exceptions, not MSR.FE0
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Léo Lam 2021-07-07 12:13:16 +02:00 committed by GitHub
parent 954f27c5d7 0642ff8b25
commit 925379cb9f
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 2 deletions
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4
Source/Core/Core/PowerPC/JitArm64/Jit.cpp
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@ -749,7 +749,7 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
LDR(IndexType::Unsigned, ARM64Reg::W30, PPC_REG, PPCSTATE_OFF(Exceptions));
TBZ(ARM64Reg::W30, IntLog2(EXCEPTION_EXTERNAL_INT), done_here);
LDR(IndexType::Unsigned, ARM64Reg::W30, PPC_REG, PPCSTATE_OFF(msr));
TBZ(ARM64Reg::W30, 11, done_here);
TBZ(ARM64Reg::W30, 15, done_here); // MSR.EE
MOVP2R(ARM64Reg::X30, &ProcessorInterface::m_InterruptCause);
LDR(IndexType::Unsigned, ARM64Reg::W30, ARM64Reg::X30, 0);
TST(ARM64Reg::W30, 23, 2);
@ -780,7 +780,7 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
FixupBranch exit = B();
SetJumpTarget(Exception);
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(msr));
TBZ(WA, 11, done_here);
TBZ(WA, 15, done_here); // MSR.EE
MOVP2R(XA, &ProcessorInterface::m_InterruptCause);
LDR(IndexType::Unsigned, WA, XA, 0);
TST(WA, 23, 2);