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Jit: Handle imm msr in EmitStoreMembase 

This makes Jit64::mtmsr more optimized in particular.
This commit is contained in:
JosJuice 2023-08-19 19:45:35 +02:00
parent ed7894924c
commit 9192128c50
5 changed files with 30 additions and 6 deletions
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16
Source/Core/Core/PowerPC/Jit64/Jit.cpp
View File

@ -498,10 +498,18 @@ void Jit64::EmitUpdateMembase()
void Jit64::EmitStoreMembase(const OpArg& msr, X64Reg scratch_reg) void Jit64::EmitStoreMembase(const OpArg& msr, X64Reg scratch_reg)
{ {
auto& memory = m_system.GetMemory(); auto& memory = m_system.GetMemory();
MOV(64, R(RMEM), ImmPtr(memory.GetLogicalBase())); if (msr.IsImm())
MOV(64, R(scratch_reg), ImmPtr(memory.GetPhysicalBase())); {
TEST(32, msr, Imm32(1 << (31 - 27))); MOV(64, R(RMEM),
CMOVcc(64, RMEM, R(scratch_reg), CC_Z); ImmPtr(UReg_MSR(msr.Imm32()).DR ? memory.GetLogicalBase() : memory.GetPhysicalBase()));
}
else
{
MOV(64, R(RMEM), ImmPtr(memory.GetLogicalBase()));
MOV(64, R(scratch_reg), ImmPtr(memory.GetPhysicalBase()));
TEST(32, msr, Imm32(1 << (31 - 27)));
CMOVcc(64, RMEM, R(scratch_reg), CC_Z);
}
MOV(64, PPCSTATE(mem_ptr), R(RMEM)); MOV(64, PPCSTATE(mem_ptr), R(RMEM));
} }

2
Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
View File

@ -439,7 +439,7 @@ void Jit64::mtmsr(UGeckoInstruction inst)
RegCache::Realize(Rs); RegCache::Realize(Rs);
MOV(32, PPCSTATE(msr), Rs); MOV(32, PPCSTATE(msr), Rs);
EmitStoreMembase(PPCSTATE(msr), RSCRATCH2); EmitStoreMembase(Rs, RSCRATCH2);
} }
gpr.Flush(); gpr.Flush();

10
Source/Core/Core/PowerPC/JitArm64/Jit.cpp
View File

@ -361,6 +361,16 @@ void JitArm64::EmitUpdateMembase()
LDR(IndexType::Unsigned, MEM_REG, PPC_REG, PPCSTATE_OFF(mem_ptr)); LDR(IndexType::Unsigned, MEM_REG, PPC_REG, PPCSTATE_OFF(mem_ptr));
} }
void JitArm64::EmitStoreMembase(u32 msr)
{
auto& memory = m_system.GetMemory();
MOVP2R(MEM_REG,
UReg_MSR(msr).DR ?
(jo.fastmem_arena ? memory.GetLogicalBase() : memory.GetLogicalPageMappingsBase()) :
(jo.fastmem_arena ? memory.GetPhysicalBase() : memory.GetPhysicalPageMappingsBase()));
STR(IndexType::Unsigned, MEM_REG, PPC_REG, PPCSTATE_OFF(mem_ptr));
}
void JitArm64::EmitStoreMembase(const ARM64Reg& msr) void JitArm64::EmitStoreMembase(const ARM64Reg& msr)
{ {
auto& memory = m_system.GetMemory(); auto& memory = m_system.GetMemory();

1
Source/Core/Core/PowerPC/JitArm64/Jit.h
View File

@ -312,6 +312,7 @@ protected:
void EndTimeProfile(JitBlock* b); void EndTimeProfile(JitBlock* b);
void EmitUpdateMembase(); void EmitUpdateMembase();
void EmitStoreMembase(u32 msr);
void EmitStoreMembase(const Arm64Gen::ARM64Reg& msr); void EmitStoreMembase(const Arm64Gen::ARM64Reg& msr);
// Exits // Exits

7
Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp
View File

@ -91,10 +91,15 @@ void JitArm64::mtmsr(UGeckoInstruction inst)
JITDISABLE(bJITSystemRegistersOff); JITDISABLE(bJITSystemRegistersOff);
FALLBACK_IF(jo.fp_exceptions); FALLBACK_IF(jo.fp_exceptions);
const bool imm_value = gpr.IsImm(inst.RS);
if (imm_value)
EmitStoreMembase(gpr.GetImm(inst.RS));
gpr.BindToRegister(inst.RS, true); gpr.BindToRegister(inst.RS, true);
STR(IndexType::Unsigned, gpr.R(inst.RS), PPC_REG, PPCSTATE_OFF(msr)); STR(IndexType::Unsigned, gpr.R(inst.RS), PPC_REG, PPCSTATE_OFF(msr));
EmitStoreMembase(gpr.R(inst.RS)); if (!imm_value)
EmitStoreMembase(gpr.R(inst.RS));
gpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG); gpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG); fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);