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Jit64: fix psq_l/st regression

This commit is contained in:
Tillmann Karras 2015-01-14 23:36:24 +01:00
parent abb083169b
commit 904a1c5558
1 changed files with 4 additions and 3 deletions
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7
Source/Core/Core/PowerPC/Jit64/Jit_LoadStorePaired.cpp
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@ -40,7 +40,8 @@ void Jit64::psq_stXX(UGeckoInstruction inst)
X64Reg addr = gpr.RX(a); X64Reg addr = gpr.RX(a);
// TODO: this is kind of ugly :/ we should probably create a universal load/store address calculation // TODO: this is kind of ugly :/ we should probably create a universal load/store address calculation
// function that handles all these weird cases, e.g. how non-fastmem loadstores clobber addresses. // function that handles all these weird cases, e.g. how non-fastmem loadstores clobber addresses.
if ((update && js.memcheck) || !SConfig::GetInstance().m_LocalCoreStartupParameter.bFastmem) bool storeAddress = (update && js.memcheck) || !SConfig::GetInstance().m_LocalCoreStartupParameter.bFastmem;
if (storeAddress)
{ {
addr = RSCRATCH2; addr = RSCRATCH2;
MOV(32, R(addr), gpr.R(a)); MOV(32, R(addr), gpr.R(a));
@ -88,11 +89,11 @@ void Jit64::psq_stXX(UGeckoInstruction inst)
} }
BitSet32 registersInUse = CallerSavedRegistersInUse(); BitSet32 registersInUse = CallerSavedRegistersInUse();
if (update && js.memcheck) if (update && storeAddress)
registersInUse[addr] = true; registersInUse[addr] = true;
SafeWriteRegToReg(RSCRATCH, addr, w ? 32 : 64, storeOffset, registersInUse); SafeWriteRegToReg(RSCRATCH, addr, w ? 32 : 64, storeOffset, registersInUse);
MemoryExceptionCheck(); MemoryExceptionCheck();
if (update && js.memcheck) if (update && storeAddress)
MOV(32, gpr.R(a), R(addr)); MOV(32, gpr.R(a), R(addr));
gpr.UnlockAll(); gpr.UnlockAll();
fpr.UnlockAll(); fpr.UnlockAll();