JitRegCache: Make member variables conform to our coding style

This commit is contained in:
Lioncash 2016-12-20 22:59:03 -05:00
parent e291e8f1a7
commit 8ece485a2f
4 changed files with 78 additions and 78 deletions

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@ -11,12 +11,12 @@ using namespace Gen;
void FPURegCache::StoreRegister(size_t preg, const OpArg& new_loc) void FPURegCache::StoreRegister(size_t preg, const OpArg& new_loc)
{ {
emit->MOVAPD(new_loc, regs[preg].location.GetSimpleReg()); m_emitter->MOVAPD(new_loc, m_regs[preg].location.GetSimpleReg());
} }
void FPURegCache::LoadRegister(size_t preg, X64Reg new_loc) void FPURegCache::LoadRegister(size_t preg, X64Reg new_loc)
{ {
emit->MOVAPD(new_loc, regs[preg].location); m_emitter->MOVAPD(new_loc, m_regs[preg].location);
} }
const X64Reg* FPURegCache::GetAllocationOrder(size_t* count) const X64Reg* FPURegCache::GetAllocationOrder(size_t* count)

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@ -11,12 +11,12 @@ using namespace Gen;
void GPRRegCache::StoreRegister(size_t preg, const OpArg& new_loc) void GPRRegCache::StoreRegister(size_t preg, const OpArg& new_loc)
{ {
emit->MOV(32, new_loc, regs[preg].location); m_emitter->MOV(32, new_loc, m_regs[preg].location);
} }
void GPRRegCache::LoadRegister(size_t preg, X64Reg new_loc) void GPRRegCache::LoadRegister(size_t preg, X64Reg new_loc)
{ {
emit->MOV(32, ::Gen::R(new_loc), regs[preg].location); m_emitter->MOV(32, ::Gen::R(new_loc), m_regs[preg].location);
} }
OpArg GPRRegCache::GetDefaultLocation(size_t reg) const OpArg GPRRegCache::GetDefaultLocation(size_t reg) const
@ -46,8 +46,8 @@ void GPRRegCache::SetImmediate32(size_t preg, u32 imm_value, bool dirty)
// "dirty" can be false to avoid redundantly flushing an immediate when // "dirty" can be false to avoid redundantly flushing an immediate when
// processing speculative constants. // processing speculative constants.
DiscardRegContentsIfCached(preg); DiscardRegContentsIfCached(preg);
regs[preg].away |= dirty; m_regs[preg].away |= dirty;
regs[preg].location = Imm32(imm_value); m_regs[preg].location = Imm32(imm_value);
} }
BitSet32 GPRRegCache::GetRegUtilization() BitSet32 GPRRegCache::GetRegUtilization()

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@ -19,24 +19,24 @@
using namespace Gen; using namespace Gen;
using namespace PowerPC; using namespace PowerPC;
RegCache::RegCache() : emit(nullptr) RegCache::RegCache()
{ {
} }
void RegCache::Start() void RegCache::Start()
{ {
for (auto& xreg : xregs) for (auto& xreg : m_xregs)
{ {
xreg.free = true; xreg.free = true;
xreg.dirty = false; xreg.dirty = false;
xreg.locked = false; xreg.locked = false;
xreg.ppcReg = INVALID_REG; xreg.ppcReg = INVALID_REG;
} }
for (size_t i = 0; i < regs.size(); i++) for (size_t i = 0; i < m_regs.size(); i++)
{ {
regs[i].location = GetDefaultLocation(i); m_regs[i].location = GetDefaultLocation(i);
regs[i].away = false; m_regs[i].away = false;
regs[i].locked = false; m_regs[i].locked = false;
} }
// todo: sort to find the most popular regs // todo: sort to find the most popular regs
@ -60,38 +60,38 @@ void RegCache::DiscardRegContentsIfCached(size_t preg)
{ {
if (IsBound(preg)) if (IsBound(preg))
{ {
X64Reg xr = regs[preg].location.GetSimpleReg(); X64Reg xr = m_regs[preg].location.GetSimpleReg();
xregs[xr].free = true; m_xregs[xr].free = true;
xregs[xr].dirty = false; m_xregs[xr].dirty = false;
xregs[xr].ppcReg = INVALID_REG; m_xregs[xr].ppcReg = INVALID_REG;
regs[preg].away = false; m_regs[preg].away = false;
regs[preg].location = GetDefaultLocation(preg); m_regs[preg].location = GetDefaultLocation(preg);
} }
} }
void RegCache::SetEmitter(XEmitter* emitter) void RegCache::SetEmitter(XEmitter* emitter)
{ {
emit = emitter; m_emitter = emitter;
} }
void RegCache::Flush(FlushMode mode, BitSet32 regsToFlush) void RegCache::Flush(FlushMode mode, BitSet32 regsToFlush)
{ {
for (size_t i = 0; i < xregs.size(); i++) for (size_t i = 0; i < m_xregs.size(); i++)
{ {
if (xregs[i].locked) if (m_xregs[i].locked)
PanicAlert("Someone forgot to unlock X64 reg %zu", i); PanicAlert("Someone forgot to unlock X64 reg %zu", i);
} }
for (unsigned int i : regsToFlush) for (unsigned int i : regsToFlush)
{ {
if (regs[i].locked) if (m_regs[i].locked)
{ {
PanicAlert("Someone forgot to unlock PPC reg %u (X64 reg %i).", i, RX(i)); PanicAlert("Someone forgot to unlock PPC reg %u (X64 reg %i).", i, RX(i));
} }
if (regs[i].away) if (m_regs[i].away)
{ {
if (regs[i].location.IsSimpleReg() || regs[i].location.IsImm()) if (m_regs[i].location.IsSimpleReg() || m_regs[i].location.IsImm())
{ {
StoreFromRegister(i, mode); StoreFromRegister(i, mode);
} }
@ -105,11 +105,11 @@ void RegCache::Flush(FlushMode mode, BitSet32 regsToFlush)
void RegCache::FlushR(X64Reg reg) void RegCache::FlushR(X64Reg reg)
{ {
if (reg >= xregs.size()) if (reg >= m_xregs.size())
PanicAlert("Flushing non existent reg"); PanicAlert("Flushing non existent reg");
if (!xregs[reg].free) if (!m_xregs[reg].free)
{ {
StoreFromRegister(xregs[reg].ppcReg); StoreFromRegister(m_xregs[reg].ppcReg);
} }
} }
@ -135,19 +135,19 @@ void RegCache::FlushLockX(X64Reg reg1, X64Reg reg2)
int RegCache::SanityCheck() const int RegCache::SanityCheck() const
{ {
for (size_t i = 0; i < regs.size(); i++) for (size_t i = 0; i < m_regs.size(); i++)
{ {
if (regs[i].away) if (m_regs[i].away)
{ {
if (regs[i].location.IsSimpleReg()) if (m_regs[i].location.IsSimpleReg())
{ {
Gen::X64Reg simple = regs[i].location.GetSimpleReg(); Gen::X64Reg simple = m_regs[i].location.GetSimpleReg();
if (xregs[simple].locked) if (m_xregs[simple].locked)
return 1; return 1;
if (xregs[simple].ppcReg != i) if (m_xregs[simple].ppcReg != i)
return 2; return 2;
} }
else if (regs[i].location.IsImm()) else if (m_regs[i].location.IsImm())
{ {
return 3; return 3;
} }
@ -158,47 +158,47 @@ int RegCache::SanityCheck() const
void RegCache::KillImmediate(size_t preg, bool doLoad, bool makeDirty) void RegCache::KillImmediate(size_t preg, bool doLoad, bool makeDirty)
{ {
if (regs[preg].away) if (m_regs[preg].away)
{ {
if (regs[preg].location.IsImm()) if (m_regs[preg].location.IsImm())
BindToRegister(preg, doLoad, makeDirty); BindToRegister(preg, doLoad, makeDirty);
else if (regs[preg].location.IsSimpleReg()) else if (m_regs[preg].location.IsSimpleReg())
xregs[RX(preg)].dirty |= makeDirty; m_xregs[RX(preg)].dirty |= makeDirty;
} }
} }
void RegCache::BindToRegister(size_t i, bool doLoad, bool makeDirty) void RegCache::BindToRegister(size_t i, bool doLoad, bool makeDirty)
{ {
if (!regs[i].away || regs[i].location.IsImm()) if (!m_regs[i].away || m_regs[i].location.IsImm())
{ {
X64Reg xr = GetFreeXReg(); X64Reg xr = GetFreeXReg();
if (xregs[xr].dirty) if (m_xregs[xr].dirty)
PanicAlert("Xreg already dirty"); PanicAlert("Xreg already dirty");
if (xregs[xr].locked) if (m_xregs[xr].locked)
PanicAlert("GetFreeXReg returned locked register"); PanicAlert("GetFreeXReg returned locked register");
xregs[xr].free = false; m_xregs[xr].free = false;
xregs[xr].ppcReg = i; m_xregs[xr].ppcReg = i;
xregs[xr].dirty = makeDirty || regs[i].away; m_xregs[xr].dirty = makeDirty || m_regs[i].away;
if (doLoad) if (doLoad)
LoadRegister(i, xr); LoadRegister(i, xr);
for (size_t j = 0; j < regs.size(); j++) for (size_t j = 0; j < m_regs.size(); j++)
{ {
if (i != j && regs[j].location.IsSimpleReg(xr)) if (i != j && m_regs[j].location.IsSimpleReg(xr))
{ {
Crash(); Crash();
} }
} }
regs[i].away = true; m_regs[i].away = true;
regs[i].location = ::Gen::R(xr); m_regs[i].location = ::Gen::R(xr);
} }
else else
{ {
// reg location must be simplereg; memory locations // reg location must be simplereg; memory locations
// and immediates are taken care of above. // and immediates are taken care of above.
xregs[RX(i)].dirty |= makeDirty; m_xregs[RX(i)].dirty |= makeDirty;
} }
if (xregs[RX(i)].locked) if (m_xregs[RX(i)].locked)
{ {
PanicAlert("Seriously WTF, this reg should have been flushed"); PanicAlert("Seriously WTF, this reg should have been flushed");
} }
@ -206,18 +206,18 @@ void RegCache::BindToRegister(size_t i, bool doLoad, bool makeDirty)
void RegCache::StoreFromRegister(size_t i, FlushMode mode) void RegCache::StoreFromRegister(size_t i, FlushMode mode)
{ {
if (regs[i].away) if (m_regs[i].away)
{ {
bool doStore; bool doStore;
if (regs[i].location.IsSimpleReg()) if (m_regs[i].location.IsSimpleReg())
{ {
X64Reg xr = RX(i); X64Reg xr = RX(i);
doStore = xregs[xr].dirty; doStore = m_xregs[xr].dirty;
if (mode == FLUSH_ALL) if (mode == FLUSH_ALL)
{ {
xregs[xr].free = true; m_xregs[xr].free = true;
xregs[xr].ppcReg = INVALID_REG; m_xregs[xr].ppcReg = INVALID_REG;
xregs[xr].dirty = false; m_xregs[xr].dirty = false;
} }
} }
else else
@ -230,21 +230,21 @@ void RegCache::StoreFromRegister(size_t i, FlushMode mode)
StoreRegister(i, newLoc); StoreRegister(i, newLoc);
if (mode == FLUSH_ALL) if (mode == FLUSH_ALL)
{ {
regs[i].location = newLoc; m_regs[i].location = newLoc;
regs[i].away = false; m_regs[i].away = false;
} }
} }
} }
const OpArg& RegCache::R(size_t preg) const const OpArg& RegCache::R(size_t preg) const
{ {
return regs[preg].location; return m_regs[preg].location;
} }
X64Reg RegCache::RX(size_t preg) const X64Reg RegCache::RX(size_t preg) const
{ {
if (IsBound(preg)) if (IsBound(preg))
return regs[preg].location.GetSimpleReg(); return m_regs[preg].location.GetSimpleReg();
PanicAlert("Unbound register - %zu", preg); PanicAlert("Unbound register - %zu", preg);
return Gen::INVALID_REG; return Gen::INVALID_REG;
@ -252,24 +252,24 @@ X64Reg RegCache::RX(size_t preg) const
void RegCache::UnlockAll() void RegCache::UnlockAll()
{ {
for (auto& reg : regs) for (auto& reg : m_regs)
reg.locked = false; reg.locked = false;
} }
void RegCache::UnlockAllX() void RegCache::UnlockAllX()
{ {
for (auto& xreg : xregs) for (auto& xreg : m_xregs)
xreg.locked = false; xreg.locked = false;
} }
bool RegCache::IsFreeX(size_t xreg) const bool RegCache::IsFreeX(size_t xreg) const
{ {
return xregs[xreg].free && !xregs[xreg].locked; return m_xregs[xreg].free && !m_xregs[xreg].locked;
} }
bool RegCache::IsBound(size_t preg) const bool RegCache::IsBound(size_t preg) const
{ {
return regs[preg].away && regs[preg].location.IsSimpleReg(); return m_regs[preg].away && m_regs[preg].location.IsSimpleReg();
} }
X64Reg RegCache::GetFreeXReg() X64Reg RegCache::GetFreeXReg()
@ -279,7 +279,7 @@ X64Reg RegCache::GetFreeXReg()
for (size_t i = 0; i < aCount; i++) for (size_t i = 0; i < aCount; i++)
{ {
X64Reg xr = aOrder[i]; X64Reg xr = aOrder[i];
if (!xregs[xr].locked && xregs[xr].free) if (!m_xregs[xr].locked && m_xregs[xr].free)
{ {
return xr; return xr;
} }
@ -293,8 +293,8 @@ X64Reg RegCache::GetFreeXReg()
for (size_t i = 0; i < aCount; i++) for (size_t i = 0; i < aCount; i++)
{ {
X64Reg xreg = (X64Reg)aOrder[i]; X64Reg xreg = (X64Reg)aOrder[i];
size_t preg = xregs[xreg].ppcReg; size_t preg = m_xregs[xreg].ppcReg;
if (xregs[xreg].locked || regs[preg].locked) if (m_xregs[xreg].locked || m_regs[preg].locked)
continue; continue;
float score = ScoreRegister(xreg); float score = ScoreRegister(xreg);
if (score < min_score) if (score < min_score)
@ -322,7 +322,7 @@ int RegCache::NumFreeRegisters()
size_t aCount; size_t aCount;
const X64Reg* aOrder = GetAllocationOrder(&aCount); const X64Reg* aOrder = GetAllocationOrder(&aCount);
for (size_t i = 0; i < aCount; i++) for (size_t i = 0; i < aCount; i++)
if (!xregs[aOrder[i]].locked && xregs[aOrder[i]].free) if (!m_xregs[aOrder[i]].locked && m_xregs[aOrder[i]].free)
count++; count++;
return count; return count;
} }
@ -331,14 +331,14 @@ int RegCache::NumFreeRegisters()
// means more bad. // means more bad.
float RegCache::ScoreRegister(X64Reg xr) float RegCache::ScoreRegister(X64Reg xr)
{ {
size_t preg = xregs[xr].ppcReg; size_t preg = m_xregs[xr].ppcReg;
float score = 0; float score = 0;
// If it's not dirty, we don't need a store to write it back to the register file, so // If it's not dirty, we don't need a store to write it back to the register file, so
// bias a bit against dirty registers. Testing shows that a bias of 2 seems roughly // bias a bit against dirty registers. Testing shows that a bias of 2 seems roughly
// right: 3 causes too many extra clobbers, while 1 saves very few clobbers relative // right: 3 causes too many extra clobbers, while 1 saves very few clobbers relative
// to the number of extra stores it causes. // to the number of extra stores it causes.
if (xregs[xr].dirty) if (m_xregs[xr].dirty)
score += 2; score += 2;
// If the register isn't actually needed in a physical register for a later instruction, // If the register isn't actually needed in a physical register for a later instruction,

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@ -73,7 +73,7 @@ public:
template <typename T> template <typename T>
void Lock(T p) void Lock(T p)
{ {
regs[p].locked = true; m_regs[p].locked = true;
} }
template <typename T, typename... Args> template <typename T, typename... Args>
void Lock(T first, Args... args) void Lock(T first, Args... args)
@ -86,9 +86,9 @@ public:
template <typename T> template <typename T>
void LockX(T x) void LockX(T x)
{ {
if (xregs[x].locked) if (m_xregs[x].locked)
PanicAlert("RegCache: x %i already locked!", x); PanicAlert("RegCache: x %i already locked!", x);
xregs[x].locked = true; m_xregs[x].locked = true;
} }
template <typename T, typename... Args> template <typename T, typename... Args>
void LockX(T first, Args... args) void LockX(T first, Args... args)
@ -100,9 +100,9 @@ public:
template <typename T> template <typename T>
void UnlockX(T x) void UnlockX(T x)
{ {
if (!xregs[x].locked) if (!m_xregs[x].locked)
PanicAlert("RegCache: x %i already unlocked!", x); PanicAlert("RegCache: x %i already unlocked!", x);
xregs[x].locked = false; m_xregs[x].locked = false;
} }
template <typename T, typename... Args> template <typename T, typename... Args>
void UnlockX(T first, Args... args) void UnlockX(T first, Args... args)
@ -128,7 +128,7 @@ protected:
float ScoreRegister(Gen::X64Reg xreg); float ScoreRegister(Gen::X64Reg xreg);
std::array<PPCCachedReg, 32> regs; std::array<PPCCachedReg, 32> m_regs;
std::array<X64CachedReg, NUM_XREGS> xregs; std::array<X64CachedReg, NUM_XREGS> m_xregs;
Gen::XEmitter* emit; Gen::XEmitter* m_emitter = nullptr;
}; };