Remove the old PPAnalyst::Flatten function that is no longer in use.
This commit is contained in:
Ryan Houdek
parent
c794dc8085
commit
8e1dfef14c
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@ -269,302 +269,6 @@ bool CanSwapAdjacentOps(const CodeOp &a, const CodeOp &b)
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return true;
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}
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// Does not yet perform inlining - although there are plans for that.
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// Returns the exit address of the next PC
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u32 Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa,
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BlockRegStats *fpa, bool &broken_block, CodeBuffer *buffer,
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int blockSize, u32* merged_addresses,
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int capacity_of_merged_addresses, int& size_of_merged_addresses)
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{
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if (capacity_of_merged_addresses < FUNCTION_FOLLOWING_THRESHOLD) {
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PanicAlert("Capacity of merged_addresses is too small!");
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}
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std::fill_n(merged_addresses, capacity_of_merged_addresses, 0);
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merged_addresses[0] = address;
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size_of_merged_addresses = 1;
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memset(st, 0, sizeof(*st));
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// Disabled the following optimization in preference of FAST_ICACHE
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//UGeckoInstruction previnst = Memory::Read_Opcode_JIT_LC(address - 4);
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//if (previnst.hex == 0x4e800020)
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// st->isFirstBlockOfFunction = true;
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gpa->any = true;
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fpa->any = false;
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for (int i = 0; i < 32; i++)
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{
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gpa->firstRead[i] = -1;
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gpa->firstWrite[i] = -1;
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gpa->numReads[i] = 0;
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gpa->numWrites[i] = 0;
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}
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u32 blockstart = address;
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int maxsize = blockSize;
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int num_inst = 0;
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int numFollows = 0;
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int numCycles = 0;
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CodeOp *code = buffer->codebuffer;
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bool foundExit = false;
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u32 return_address = 0;
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// Do analysis of the code, look for dependencies etc
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int numSystemInstructions = 0;
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for (int i = 0; i < maxsize; i++)
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{
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UGeckoInstruction inst = JitInterface::Read_Opcode_JIT(address);
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if (inst.hex != 0)
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{
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num_inst++;
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memset(&code[i], 0, sizeof(CodeOp));
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GekkoOPInfo *opinfo = GetOpInfo(inst);
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code[i].opinfo = opinfo;
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// FIXME: code[i].address may not be correct due to CST1 code.
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code[i].address = address;
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code[i].inst = inst;
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code[i].branchTo = -1;
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code[i].branchToIndex = -1;
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code[i].skip = false;
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numCycles += opinfo->numCycles;
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code[i].wantsCR0 = false;
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code[i].wantsCR1 = false;
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code[i].wantsPS1 = false;
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int flags = opinfo->flags;
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if (flags & FL_USE_FPU)
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fpa->any = true;
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if (flags & FL_TIMER)
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gpa->anyTimer = true;
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// Does the instruction output CR0?
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if (flags & FL_RC_BIT)
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code[i].outputCR0 = inst.hex & 1; //todo fix
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else if ((flags & FL_SET_CRn) && inst.CRFD == 0)
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code[i].outputCR0 = true;
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else
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code[i].outputCR0 = (flags & FL_SET_CR0) ? true : false;
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// Does the instruction output CR1?
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if (flags & FL_RC_BIT_F)
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code[i].outputCR1 = inst.hex & 1; //todo fix
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else if ((flags & FL_SET_CRn) && inst.CRFD == 1)
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code[i].outputCR1 = true;
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else
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code[i].outputCR1 = (flags & FL_SET_CR1) ? true : false;
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int numOut = 0;
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int numIn = 0;
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if (flags & FL_OUT_A)
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{
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code[i].regsOut[numOut++] = inst.RA;
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gpa->SetOutputRegister(inst.RA, i);
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}
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if (flags & FL_OUT_D)
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{
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code[i].regsOut[numOut++] = inst.RD;
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gpa->SetOutputRegister(inst.RD, i);
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}
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if (flags & FL_OUT_S)
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{
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code[i].regsOut[numOut++] = inst.RS;
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gpa->SetOutputRegister(inst.RS, i);
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}
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if ((flags & FL_IN_A) || ((flags & FL_IN_A0) && inst.RA != 0))
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{
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code[i].regsIn[numIn++] = inst.RA;
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gpa->SetInputRegister(inst.RA, i);
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}
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if (flags & FL_IN_B)
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{
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code[i].regsIn[numIn++] = inst.RB;
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gpa->SetInputRegister(inst.RB, i);
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}
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if (flags & FL_IN_C)
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{
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code[i].regsIn[numIn++] = inst.RC;
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gpa->SetInputRegister(inst.RC, i);
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}
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if (flags & FL_IN_S)
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{
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code[i].regsIn[numIn++] = inst.RS;
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gpa->SetInputRegister(inst.RS, i);
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}
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// Set remaining register slots as unused (-1)
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for (int j = numIn; j < 3; j++)
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code[i].regsIn[j] = -1;
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for (int j = numOut; j < 2; j++)
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code[i].regsOut[j] = -1;
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for (int j = 0; j < 3; j++)
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code[i].fregsIn[j] = -1;
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code[i].fregOut = -1;
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switch (opinfo->type)
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{
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case OPTYPE_INTEGER:
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case OPTYPE_LOAD:
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case OPTYPE_STORE:
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case OPTYPE_LOADFP:
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case OPTYPE_STOREFP:
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break;
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case OPTYPE_FPU:
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break;
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case OPTYPE_BRANCH:
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if (code[i].inst.hex == 0x4e800020)
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{
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// For analysis purposes, we can assume that blr eats flags.
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code[i].outputCR0 = true;
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code[i].outputCR1 = true;
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}
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break;
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case OPTYPE_SYSTEM:
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case OPTYPE_SYSTEMFP:
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numSystemInstructions++;
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break;
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}
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bool follow = false;
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u32 destination = 0;
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if (inst.OPCD == 18 && blockSize > 1)
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{
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//Is bx - should we inline? yes!
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if (inst.AA)
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destination = SignExt26(inst.LI << 2);
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else
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destination = address + SignExt26(inst.LI << 2);
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if (destination != blockstart)
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follow = true;
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}
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else if (inst.OPCD == 19 && inst.SUBOP10 == 16 &&
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(inst.BO & (1 << 4)) && (inst.BO & (1 << 2)) &&
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return_address != 0)
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{
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// bclrx with unconditional branch = return
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follow = true;
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destination = return_address;
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return_address = 0;
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if (inst.LK)
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return_address = address + 4;
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}
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else if (inst.OPCD == 31 && inst.SUBOP10 == 467)
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{
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// mtspr
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const u32 index = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
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if (index == SPR_LR) {
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// We give up to follow the return address
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// because we have to check the register usage.
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return_address = 0;
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}
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}
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if (follow)
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numFollows++;
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// TODO: Find the optimal value for FUNCTION_FOLLOWING_THRESHOLD.
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// If it is small, the performance will be down.
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// If it is big, the size of generated code will be big and
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// cache clearning will happen many times.
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// TODO: Investivate the reason why
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// "0" is fastest in some games, MP2 for example.
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if (numFollows > FUNCTION_FOLLOWING_THRESHOLD)
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follow = false;
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if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bMergeBlocks) {
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follow = false;
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}
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if (!follow)
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{
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if (opinfo->flags & FL_ENDBLOCK) //right now we stop early
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{
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foundExit = true;
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break;
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}
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address += 4;
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}
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else
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{
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// We don't "code[i].skip = true" here
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// because bx may store a certain value to the link register.
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// Instead, we skip a part of bx in Jit**::bx().
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address = destination;
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merged_addresses[size_of_merged_addresses++] = address;
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}
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}
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else
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{
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// ISI exception or other critical memory exception occurred (game over)
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break;
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}
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}
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st->numCycles = numCycles;
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// Instruction Reordering Pass
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if (num_inst > 1)
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{
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// Bubble down compares towards branches, so that they can be merged.
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// -2: -1 for the pair, -1 for not swapping with the final instruction which is probably the branch.
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for (int i = 0; i < num_inst - 2; i++)
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{
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CodeOp &a = code[i];
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CodeOp &b = code[i + 1];
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// All integer compares can be reordered.
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if ((a.inst.OPCD == 10 || a.inst.OPCD == 11) ||
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(a.inst.OPCD == 31 && (a.inst.SUBOP10 == 0 || a.inst.SUBOP10 == 32)))
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{
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// Got a compare instruction.
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if (CanSwapAdjacentOps(a, b)) {
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// Alright, let's bubble it down!
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CodeOp c = a;
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a = b;
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b = c;
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}
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}
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}
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}
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if (!foundExit && num_inst > 0)
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{
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// A broken block is a block that does not end in a branch
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broken_block = true;
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}
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// Scan for CR0 dependency
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// assume next block wants CR0 to be safe
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bool wantsCR0 = true;
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bool wantsCR1 = true;
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bool wantsPS1 = true;
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for (int i = num_inst - 1; i >= 0; i--)
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{
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if (code[i].outputCR0)
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wantsCR0 = false;
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if (code[i].outputCR1)
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wantsCR1 = false;
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if (code[i].outputPS1)
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wantsPS1 = false;
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wantsCR0 |= code[i].wantsCR0;
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wantsCR1 |= code[i].wantsCR1;
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wantsPS1 |= code[i].wantsPS1;
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code[i].wantsCR0 = wantsCR0;
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code[i].wantsCR1 = wantsCR1;
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code[i].wantsPS1 = wantsPS1;
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}
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*realsize = num_inst;
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// ...
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return address;
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}
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// Most functions that are relevant to analyze should be
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// called by another function. Therefore, let's scan the
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// entire space for bl operations and find what functions
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@ -175,10 +175,6 @@ public:
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u32 Analyze(u32 address, CodeBlock *block, CodeBuffer *buffer, u32 blockSize);
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};
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u32 Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa,
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BlockRegStats *fpa, bool &broken_block, CodeBuffer *buffer,
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int blockSize, u32* merged_addresses,
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int capacity_of_merged_addresses, int& size_of_merged_addresses);
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void LogFunctionCall(u32 addr);
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void FindFunctions(u32 startAddr, u32 endAddr, PPCSymbolDB *func_db);
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bool AnalyzeFunction(u32 startAddr, Symbol &func, int max_size = 0);
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