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@ -24,14 +24,14 @@
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namespace CommandProcessor
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{
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static bool IsOnThread(Core::System& system)
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static bool IsOnThread(const Core::System& system)
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{
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return system.IsDualCoreMode();
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}
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static void UpdateInterrupts_Wrapper(Core::System& system, u64 userdata, s64 cyclesLate)
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{
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system.GetCommandProcessor().UpdateInterrupts(system, userdata);
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system.GetCommandProcessor().UpdateInterrupts(userdata);
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}
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void SCPFifoStruct::Init()
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@ -105,7 +105,11 @@ static inline void WriteHigh(std::atomic<u32>& reg, u16 highbits)
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std::memory_order_relaxed);
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}
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void CommandProcessorManager::Init(Core::System& system)
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CommandProcessorManager::CommandProcessorManager(Core::System& system) : m_system{system}
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{
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}
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void CommandProcessorManager::Init()
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{
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m_cp_status_reg.Hex = 0;
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m_cp_status_reg.CommandIdle = 1;
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@ -130,7 +134,7 @@ void CommandProcessorManager::Init(Core::System& system)
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m_interrupt_waiting.Clear();
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m_event_type_update_interrupts =
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system.GetCoreTiming().RegisterEvent("CPInterrupt", UpdateInterrupts_Wrapper);
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m_system.GetCoreTiming().RegisterEvent("CPInterrupt", UpdateInterrupts_Wrapper);
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}
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u32 GetPhysicalAddressMask()
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@ -140,15 +144,13 @@ u32 GetPhysicalAddressMask()
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return SConfig::GetInstance().bWii ? 0x1fffffff : 0x03ffffff;
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}
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void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping* mmio, u32 base)
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void CommandProcessorManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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{
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constexpr u16 WMASK_NONE = 0x0000;
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constexpr u16 WMASK_ALL = 0xffff;
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constexpr u16 WMASK_LO_ALIGN_32BIT = 0xffe0;
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const u16 WMASK_HI_RESTRICT = GetPhysicalAddressMask() >> 16;
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auto& fifo = m_fifo;
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struct
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{
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u32 addr;
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@ -166,25 +168,27 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
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{FIFO_BOUNDING_BOX_RIGHT, &m_bbox_right, true, WMASK_NONE},
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{FIFO_BOUNDING_BOX_TOP, &m_bbox_top, true, WMASK_NONE},
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{FIFO_BOUNDING_BOX_BOTTOM, &m_bbox_bottom, true, WMASK_NONE},
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{FIFO_BASE_LO, MMIO::Utils::LowPart(&fifo.CPBase), false, WMASK_LO_ALIGN_32BIT},
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{FIFO_BASE_HI, MMIO::Utils::HighPart(&fifo.CPBase), false, WMASK_HI_RESTRICT},
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{FIFO_END_LO, MMIO::Utils::LowPart(&fifo.CPEnd), false, WMASK_LO_ALIGN_32BIT},
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{FIFO_END_HI, MMIO::Utils::HighPart(&fifo.CPEnd), false, WMASK_HI_RESTRICT},
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{FIFO_HI_WATERMARK_LO, MMIO::Utils::LowPart(&fifo.CPHiWatermark), false,
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{FIFO_BASE_LO, MMIO::Utils::LowPart(&m_fifo.CPBase), false, WMASK_LO_ALIGN_32BIT},
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{FIFO_BASE_HI, MMIO::Utils::HighPart(&m_fifo.CPBase), false, WMASK_HI_RESTRICT},
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{FIFO_END_LO, MMIO::Utils::LowPart(&m_fifo.CPEnd), false, WMASK_LO_ALIGN_32BIT},
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{FIFO_END_HI, MMIO::Utils::HighPart(&m_fifo.CPEnd), false, WMASK_HI_RESTRICT},
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{FIFO_HI_WATERMARK_LO, MMIO::Utils::LowPart(&m_fifo.CPHiWatermark), false,
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WMASK_LO_ALIGN_32BIT},
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{FIFO_HI_WATERMARK_HI, MMIO::Utils::HighPart(&fifo.CPHiWatermark), false, WMASK_HI_RESTRICT},
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{FIFO_LO_WATERMARK_LO, MMIO::Utils::LowPart(&fifo.CPLoWatermark), false,
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{FIFO_HI_WATERMARK_HI, MMIO::Utils::HighPart(&m_fifo.CPHiWatermark), false,
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WMASK_HI_RESTRICT},
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{FIFO_LO_WATERMARK_LO, MMIO::Utils::LowPart(&m_fifo.CPLoWatermark), false,
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WMASK_LO_ALIGN_32BIT},
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{FIFO_LO_WATERMARK_HI, MMIO::Utils::HighPart(&fifo.CPLoWatermark), false, WMASK_HI_RESTRICT},
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{FIFO_LO_WATERMARK_HI, MMIO::Utils::HighPart(&m_fifo.CPLoWatermark), false,
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WMASK_HI_RESTRICT},
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// FIFO_RW_DISTANCE has some complex read code different for
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// single/dual core.
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{FIFO_WRITE_POINTER_LO, MMIO::Utils::LowPart(&fifo.CPWritePointer), false,
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{FIFO_WRITE_POINTER_LO, MMIO::Utils::LowPart(&m_fifo.CPWritePointer), false,
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WMASK_LO_ALIGN_32BIT},
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{FIFO_WRITE_POINTER_HI, MMIO::Utils::HighPart(&fifo.CPWritePointer), false,
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{FIFO_WRITE_POINTER_HI, MMIO::Utils::HighPart(&m_fifo.CPWritePointer), false,
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WMASK_HI_RESTRICT},
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// FIFO_READ_POINTER has different code for single/dual core.
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{FIFO_BP_LO, MMIO::Utils::LowPart(&fifo.CPBreakpoint), false, WMASK_LO_ALIGN_32BIT},
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{FIFO_BP_HI, MMIO::Utils::HighPart(&fifo.CPBreakpoint), false, WMASK_HI_RESTRICT},
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{FIFO_BP_LO, MMIO::Utils::LowPart(&m_fifo.CPBreakpoint), false, WMASK_LO_ALIGN_32BIT},
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{FIFO_BP_HI, MMIO::Utils::HighPart(&m_fifo.CPBreakpoint), false, WMASK_HI_RESTRICT},
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};
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for (auto& mapped_var : directly_mapped_vars)
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@ -225,7 +229,7 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
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mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](Core::System& system_, u32) {
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auto& cp = system_.GetCommandProcessor();
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system_.GetFifo().SyncGPUForRegisterAccess();
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cp.SetCpStatusRegister(system_);
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cp.SetCpStatusRegister();
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return cp.m_cp_status_reg.Hex;
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}),
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MMIO::InvalidWrite<u16>());
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@ -235,7 +239,7 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
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auto& cp = system_.GetCommandProcessor();
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UCPCtrlReg tmp(val);
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cp.m_cp_ctrl_reg.Hex = tmp.Hex;
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cp.SetCpControlRegister(system_);
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cp.SetCpControlRegister();
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system_.GetFifo().RunGpu();
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}));
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@ -251,7 +255,7 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
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mmio->Register(base | PERF_SELECT, MMIO::InvalidRead<u16>(), MMIO::Nop<u16>());
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// Some MMIOs have different handlers for single core vs. dual core mode.
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const bool is_on_thread = IsOnThread(system);
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const bool is_on_thread = IsOnThread(m_system);
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MMIO::ReadHandlingMethod<u16>* fifo_rw_distance_lo_r;
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if (is_on_thread)
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{
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@ -274,10 +278,11 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
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}
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else
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{
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fifo_rw_distance_lo_r = MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance));
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fifo_rw_distance_lo_r =
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MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&m_fifo.CPReadWriteDistance));
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}
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mmio->Register(base | FIFO_RW_DISTANCE_LO, fifo_rw_distance_lo_r,
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MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance),
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MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&m_fifo.CPReadWriteDistance),
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WMASK_LO_ALIGN_32BIT));
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MMIO::ReadHandlingMethod<u16>* fifo_rw_distance_hi_r;
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@ -321,9 +326,9 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
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mmio->Register(
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base | FIFO_READ_POINTER_LO,
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is_on_thread ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) :
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MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer)),
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MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer), WMASK_LO_ALIGN_32BIT));
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is_on_thread ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&m_fifo.SafeCPReadPointer)) :
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MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&m_fifo.CPReadPointer)),
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MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&m_fifo.CPReadPointer), WMASK_LO_ALIGN_32BIT));
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MMIO::ReadHandlingMethod<u16>* fifo_read_hi_r;
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MMIO::WriteHandlingMethod<u16>* fifo_read_hi_w;
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@ -360,103 +365,101 @@ void CommandProcessorManager::RegisterMMIO(Core::System& system, MMIO::Mapping*
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mmio->Register(base | FIFO_READ_POINTER_HI, fifo_read_hi_r, fifo_read_hi_w);
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}
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void CommandProcessorManager::GatherPipeBursted(Core::System& system)
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void CommandProcessorManager::GatherPipeBursted()
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{
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auto& fifo = m_fifo;
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SetCPStatusFromCPU();
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SetCPStatusFromCPU(system);
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auto& processor_interface = system.GetProcessorInterface();
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auto& processor_interface = m_system.GetProcessorInterface();
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// if we aren't linked, we don't care about gather pipe data
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if (!m_cp_ctrl_reg.GPLinkEnable)
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{
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if (IsOnThread(system) && !system.GetFifo().UseDeterministicGPUThread())
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if (IsOnThread(m_system) && !m_system.GetFifo().UseDeterministicGPUThread())
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{
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// In multibuffer mode is not allowed write in the same FIFO attached to the GPU.
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// Fix Pokemon XD in DC mode.
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if ((processor_interface.m_fifo_cpu_end == fifo.CPEnd.load(std::memory_order_relaxed)) &&
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(processor_interface.m_fifo_cpu_base == fifo.CPBase.load(std::memory_order_relaxed)) &&
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fifo.CPReadWriteDistance.load(std::memory_order_relaxed) > 0)
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if ((processor_interface.m_fifo_cpu_end == m_fifo.CPEnd.load(std::memory_order_relaxed)) &&
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(processor_interface.m_fifo_cpu_base == m_fifo.CPBase.load(std::memory_order_relaxed)) &&
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m_fifo.CPReadWriteDistance.load(std::memory_order_relaxed) > 0)
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{
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system.GetFifo().FlushGpu();
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m_system.GetFifo().FlushGpu();
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}
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}
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system.GetFifo().RunGpu();
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m_system.GetFifo().RunGpu();
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return;
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}
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// update the fifo pointer
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if (fifo.CPWritePointer.load(std::memory_order_relaxed) ==
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fifo.CPEnd.load(std::memory_order_relaxed))
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if (m_fifo.CPWritePointer.load(std::memory_order_relaxed) ==
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m_fifo.CPEnd.load(std::memory_order_relaxed))
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{
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fifo.CPWritePointer.store(fifo.CPBase, std::memory_order_relaxed);
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m_fifo.CPWritePointer.store(m_fifo.CPBase, std::memory_order_relaxed);
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}
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else
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{
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fifo.CPWritePointer.fetch_add(GPFifo::GATHER_PIPE_SIZE, std::memory_order_relaxed);
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m_fifo.CPWritePointer.fetch_add(GPFifo::GATHER_PIPE_SIZE, std::memory_order_relaxed);
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}
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if (m_cp_ctrl_reg.GPReadEnable && m_cp_ctrl_reg.GPLinkEnable)
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{
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processor_interface.m_fifo_cpu_write_pointer =
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fifo.CPWritePointer.load(std::memory_order_relaxed);
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processor_interface.m_fifo_cpu_base = fifo.CPBase.load(std::memory_order_relaxed);
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processor_interface.m_fifo_cpu_end = fifo.CPEnd.load(std::memory_order_relaxed);
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m_fifo.CPWritePointer.load(std::memory_order_relaxed);
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processor_interface.m_fifo_cpu_base = m_fifo.CPBase.load(std::memory_order_relaxed);
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processor_interface.m_fifo_cpu_end = m_fifo.CPEnd.load(std::memory_order_relaxed);
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}
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// If the game is running close to overflowing, make the exception checking more frequent.
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if (fifo.bFF_HiWatermark.load(std::memory_order_relaxed) != 0)
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system.GetCoreTiming().ForceExceptionCheck(0);
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if (m_fifo.bFF_HiWatermark.load(std::memory_order_relaxed) != 0)
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m_system.GetCoreTiming().ForceExceptionCheck(0);
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fifo.CPReadWriteDistance.fetch_add(GPFifo::GATHER_PIPE_SIZE, std::memory_order_seq_cst);
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m_fifo.CPReadWriteDistance.fetch_add(GPFifo::GATHER_PIPE_SIZE, std::memory_order_seq_cst);
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system.GetFifo().RunGpu();
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m_system.GetFifo().RunGpu();
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ASSERT_MSG(COMMANDPROCESSOR,
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fifo.CPReadWriteDistance.load(std::memory_order_relaxed) <=
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fifo.CPEnd.load(std::memory_order_relaxed) -
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fifo.CPBase.load(std::memory_order_relaxed),
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m_fifo.CPReadWriteDistance.load(std::memory_order_relaxed) <=
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m_fifo.CPEnd.load(std::memory_order_relaxed) -
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m_fifo.CPBase.load(std::memory_order_relaxed),
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"FIFO is overflowed by GatherPipe !\nCPU thread is too fast!");
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// check if we are in sync
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ASSERT_MSG(COMMANDPROCESSOR,
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fifo.CPWritePointer.load(std::memory_order_relaxed) ==
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m_fifo.CPWritePointer.load(std::memory_order_relaxed) ==
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processor_interface.m_fifo_cpu_write_pointer,
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"FIFOs linked but out of sync");
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ASSERT_MSG(COMMANDPROCESSOR,
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fifo.CPBase.load(std::memory_order_relaxed) == processor_interface.m_fifo_cpu_base,
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m_fifo.CPBase.load(std::memory_order_relaxed) == processor_interface.m_fifo_cpu_base,
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"FIFOs linked but out of sync");
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ASSERT_MSG(COMMANDPROCESSOR,
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fifo.CPEnd.load(std::memory_order_relaxed) == processor_interface.m_fifo_cpu_end,
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m_fifo.CPEnd.load(std::memory_order_relaxed) == processor_interface.m_fifo_cpu_end,
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"FIFOs linked but out of sync");
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}
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|
void CommandProcessorManager::UpdateInterrupts(Core::System& system, u64 userdata)
|
|
|
|
|
void CommandProcessorManager::UpdateInterrupts(u64 userdata)
|
|
|
|
|
{
|
|
|
|
|
if (userdata)
|
|
|
|
|
{
|
|
|
|
|
m_interrupt_set.Set();
|
|
|
|
|
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Interrupt set");
|
|
|
|
|
system.GetProcessorInterface().SetInterrupt(INT_CAUSE_CP, true);
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|
|
|
|
m_system.GetProcessorInterface().SetInterrupt(INT_CAUSE_CP, true);
|
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|
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|
}
|
|
|
|
|
else
|
|
|
|
|
{
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|
m_interrupt_set.Clear();
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|
|
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Interrupt cleared");
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|
system.GetProcessorInterface().SetInterrupt(INT_CAUSE_CP, false);
|
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|
m_system.GetProcessorInterface().SetInterrupt(INT_CAUSE_CP, false);
|
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|
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|
}
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|
system.GetCoreTiming().ForceExceptionCheck(0);
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|
m_system.GetCoreTiming().ForceExceptionCheck(0);
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|
m_interrupt_waiting.Clear();
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|
system.GetFifo().RunGpu();
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|
m_system.GetFifo().RunGpu();
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|
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|
}
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|
void CommandProcessorManager::UpdateInterruptsFromVideoBackend(Core::System& system, u64 userdata)
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|
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|
void CommandProcessorManager::UpdateInterruptsFromVideoBackend(u64 userdata)
|
|
|
|
|
{
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|
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|
if (!system.GetFifo().UseDeterministicGPUThread())
|
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|
|
|
if (!m_system.GetFifo().UseDeterministicGPUThread())
|
|
|
|
|
{
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|
system.GetCoreTiming().ScheduleEvent(0, m_event_type_update_interrupts, userdata,
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|
|
|
CoreTiming::FromThread::NON_CPU);
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|
|
|
m_system.GetCoreTiming().ScheduleEvent(0, m_event_type_update_interrupts, userdata,
|
|
|
|
|
CoreTiming::FromThread::NON_CPU);
|
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|
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|
}
|
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|
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|
}
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|
@ -465,22 +468,20 @@ bool CommandProcessorManager::IsInterruptWaiting() const
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|
return m_interrupt_waiting.IsSet();
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|
}
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|
void CommandProcessorManager::SetCPStatusFromGPU(Core::System& system)
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|
|
|
void CommandProcessorManager::SetCPStatusFromGPU()
|
|
|
|
|
{
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|
|
auto& fifo = m_fifo;
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|
|
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|
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|
// breakpoint
|
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|
|
|
const bool breakpoint = fifo.bFF_Breakpoint.load(std::memory_order_relaxed);
|
|
|
|
|
if (fifo.bFF_BPEnable.load(std::memory_order_relaxed) != 0)
|
|
|
|
|
const bool breakpoint = m_fifo.bFF_Breakpoint.load(std::memory_order_relaxed);
|
|
|
|
|
if (m_fifo.bFF_BPEnable.load(std::memory_order_relaxed) != 0)
|
|
|
|
|
{
|
|
|
|
|
if (fifo.CPBreakpoint.load(std::memory_order_relaxed) ==
|
|
|
|
|
fifo.CPReadPointer.load(std::memory_order_relaxed))
|
|
|
|
|
if (m_fifo.CPBreakpoint.load(std::memory_order_relaxed) ==
|
|
|
|
|
m_fifo.CPReadPointer.load(std::memory_order_relaxed))
|
|
|
|
|
{
|
|
|
|
|
if (!breakpoint)
|
|
|
|
|
{
|
|
|
|
|
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Hit breakpoint at {}",
|
|
|
|
|
fifo.CPReadPointer.load(std::memory_order_relaxed));
|
|
|
|
|
fifo.bFF_Breakpoint.store(1, std::memory_order_relaxed);
|
|
|
|
|
m_fifo.CPReadPointer.load(std::memory_order_relaxed));
|
|
|
|
|
m_fifo.bFF_Breakpoint.store(1, std::memory_order_relaxed);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
@ -488,8 +489,8 @@ void CommandProcessorManager::SetCPStatusFromGPU(Core::System& system)
|
|
|
|
|
if (breakpoint)
|
|
|
|
|
{
|
|
|
|
|
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Cleared breakpoint at {}",
|
|
|
|
|
fifo.CPReadPointer.load(std::memory_order_relaxed));
|
|
|
|
|
fifo.bFF_Breakpoint.store(0, std::memory_order_relaxed);
|
|
|
|
|
m_fifo.CPReadPointer.load(std::memory_order_relaxed));
|
|
|
|
|
m_fifo.bFF_Breakpoint.store(0, std::memory_order_relaxed);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
@ -498,101 +499,97 @@ void CommandProcessorManager::SetCPStatusFromGPU(Core::System& system)
|
|
|
|
|
if (breakpoint)
|
|
|
|
|
{
|
|
|
|
|
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Cleared breakpoint at {}",
|
|
|
|
|
fifo.CPReadPointer.load(std::memory_order_relaxed));
|
|
|
|
|
fifo.bFF_Breakpoint = false;
|
|
|
|
|
m_fifo.CPReadPointer.load(std::memory_order_relaxed));
|
|
|
|
|
m_fifo.bFF_Breakpoint = false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// overflow & underflow check
|
|
|
|
|
fifo.bFF_HiWatermark.store(
|
|
|
|
|
(fifo.CPReadWriteDistance.load(std::memory_order_relaxed) > fifo.CPHiWatermark),
|
|
|
|
|
m_fifo.bFF_HiWatermark.store(
|
|
|
|
|
(m_fifo.CPReadWriteDistance.load(std::memory_order_relaxed) > m_fifo.CPHiWatermark),
|
|
|
|
|
std::memory_order_relaxed);
|
|
|
|
|
fifo.bFF_LoWatermark.store(
|
|
|
|
|
(fifo.CPReadWriteDistance.load(std::memory_order_relaxed) < fifo.CPLoWatermark),
|
|
|
|
|
m_fifo.bFF_LoWatermark.store(
|
|
|
|
|
(m_fifo.CPReadWriteDistance.load(std::memory_order_relaxed) < m_fifo.CPLoWatermark),
|
|
|
|
|
std::memory_order_relaxed);
|
|
|
|
|
|
|
|
|
|
bool bpInt = fifo.bFF_Breakpoint.load(std::memory_order_relaxed) &&
|
|
|
|
|
fifo.bFF_BPInt.load(std::memory_order_relaxed);
|
|
|
|
|
bool ovfInt = fifo.bFF_HiWatermark.load(std::memory_order_relaxed) &&
|
|
|
|
|
fifo.bFF_HiWatermarkInt.load(std::memory_order_relaxed);
|
|
|
|
|
bool undfInt = fifo.bFF_LoWatermark.load(std::memory_order_relaxed) &&
|
|
|
|
|
fifo.bFF_LoWatermarkInt.load(std::memory_order_relaxed);
|
|
|
|
|
bool bpInt = m_fifo.bFF_Breakpoint.load(std::memory_order_relaxed) &&
|
|
|
|
|
m_fifo.bFF_BPInt.load(std::memory_order_relaxed);
|
|
|
|
|
bool ovfInt = m_fifo.bFF_HiWatermark.load(std::memory_order_relaxed) &&
|
|
|
|
|
m_fifo.bFF_HiWatermarkInt.load(std::memory_order_relaxed);
|
|
|
|
|
bool undfInt = m_fifo.bFF_LoWatermark.load(std::memory_order_relaxed) &&
|
|
|
|
|
m_fifo.bFF_LoWatermarkInt.load(std::memory_order_relaxed);
|
|
|
|
|
|
|
|
|
|
bool interrupt = (bpInt || ovfInt || undfInt) && m_cp_ctrl_reg.GPReadEnable;
|
|
|
|
|
|
|
|
|
|
if (interrupt != m_interrupt_set.IsSet() && !m_interrupt_waiting.IsSet())
|
|
|
|
|
{
|
|
|
|
|
u64 userdata = interrupt ? 1 : 0;
|
|
|
|
|
if (IsOnThread(system))
|
|
|
|
|
const u64 userdata = interrupt ? 1 : 0;
|
|
|
|
|
if (IsOnThread(m_system))
|
|
|
|
|
{
|
|
|
|
|
if (!interrupt || bpInt || undfInt || ovfInt)
|
|
|
|
|
{
|
|
|
|
|
// Schedule the interrupt asynchronously
|
|
|
|
|
m_interrupt_waiting.Set();
|
|
|
|
|
UpdateInterruptsFromVideoBackend(system, userdata);
|
|
|
|
|
UpdateInterruptsFromVideoBackend(userdata);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
UpdateInterrupts(system, userdata);
|
|
|
|
|
UpdateInterrupts(userdata);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void CommandProcessorManager::SetCPStatusFromCPU(Core::System& system)
|
|
|
|
|
void CommandProcessorManager::SetCPStatusFromCPU()
|
|
|
|
|
{
|
|
|
|
|
auto& fifo = m_fifo;
|
|
|
|
|
|
|
|
|
|
// overflow & underflow check
|
|
|
|
|
fifo.bFF_HiWatermark.store(
|
|
|
|
|
(fifo.CPReadWriteDistance.load(std::memory_order_relaxed) > fifo.CPHiWatermark),
|
|
|
|
|
m_fifo.bFF_HiWatermark.store(
|
|
|
|
|
(m_fifo.CPReadWriteDistance.load(std::memory_order_relaxed) > m_fifo.CPHiWatermark),
|
|
|
|
|
std::memory_order_relaxed);
|
|
|
|
|
fifo.bFF_LoWatermark.store(
|
|
|
|
|
(fifo.CPReadWriteDistance.load(std::memory_order_relaxed) < fifo.CPLoWatermark),
|
|
|
|
|
m_fifo.bFF_LoWatermark.store(
|
|
|
|
|
(m_fifo.CPReadWriteDistance.load(std::memory_order_relaxed) < m_fifo.CPLoWatermark),
|
|
|
|
|
std::memory_order_relaxed);
|
|
|
|
|
|
|
|
|
|
bool bpInt = fifo.bFF_Breakpoint.load(std::memory_order_relaxed) &&
|
|
|
|
|
fifo.bFF_BPInt.load(std::memory_order_relaxed);
|
|
|
|
|
bool ovfInt = fifo.bFF_HiWatermark.load(std::memory_order_relaxed) &&
|
|
|
|
|
fifo.bFF_HiWatermarkInt.load(std::memory_order_relaxed);
|
|
|
|
|
bool undfInt = fifo.bFF_LoWatermark.load(std::memory_order_relaxed) &&
|
|
|
|
|
fifo.bFF_LoWatermarkInt.load(std::memory_order_relaxed);
|
|
|
|
|
bool bpInt = m_fifo.bFF_Breakpoint.load(std::memory_order_relaxed) &&
|
|
|
|
|
m_fifo.bFF_BPInt.load(std::memory_order_relaxed);
|
|
|
|
|
bool ovfInt = m_fifo.bFF_HiWatermark.load(std::memory_order_relaxed) &&
|
|
|
|
|
m_fifo.bFF_HiWatermarkInt.load(std::memory_order_relaxed);
|
|
|
|
|
bool undfInt = m_fifo.bFF_LoWatermark.load(std::memory_order_relaxed) &&
|
|
|
|
|
m_fifo.bFF_LoWatermarkInt.load(std::memory_order_relaxed);
|
|
|
|
|
|
|
|
|
|
bool interrupt = (bpInt || ovfInt || undfInt) && m_cp_ctrl_reg.GPReadEnable;
|
|
|
|
|
|
|
|
|
|
if (interrupt != m_interrupt_set.IsSet() && !m_interrupt_waiting.IsSet())
|
|
|
|
|
{
|
|
|
|
|
u64 userdata = interrupt ? 1 : 0;
|
|
|
|
|
if (IsOnThread(system))
|
|
|
|
|
const u64 userdata = interrupt ? 1 : 0;
|
|
|
|
|
if (IsOnThread(m_system))
|
|
|
|
|
{
|
|
|
|
|
if (!interrupt || bpInt || undfInt || ovfInt)
|
|
|
|
|
{
|
|
|
|
|
m_interrupt_set.Set(interrupt);
|
|
|
|
|
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Interrupt set");
|
|
|
|
|
system.GetProcessorInterface().SetInterrupt(INT_CAUSE_CP, interrupt);
|
|
|
|
|
m_system.GetProcessorInterface().SetInterrupt(INT_CAUSE_CP, interrupt);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
UpdateInterrupts(system, userdata);
|
|
|
|
|
UpdateInterrupts(userdata);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void CommandProcessorManager::SetCpStatusRegister(Core::System& system)
|
|
|
|
|
void CommandProcessorManager::SetCpStatusRegister()
|
|
|
|
|
{
|
|
|
|
|
const auto& fifo = m_fifo;
|
|
|
|
|
|
|
|
|
|
// Here always there is one fifo attached to the GPU
|
|
|
|
|
m_cp_status_reg.Breakpoint = fifo.bFF_Breakpoint.load(std::memory_order_relaxed);
|
|
|
|
|
m_cp_status_reg.ReadIdle = !fifo.CPReadWriteDistance.load(std::memory_order_relaxed) ||
|
|
|
|
|
(fifo.CPReadPointer.load(std::memory_order_relaxed) ==
|
|
|
|
|
fifo.CPWritePointer.load(std::memory_order_relaxed));
|
|
|
|
|
m_cp_status_reg.CommandIdle = !fifo.CPReadWriteDistance.load(std::memory_order_relaxed) ||
|
|
|
|
|
Fifo::AtBreakpoint(system) ||
|
|
|
|
|
!fifo.bFF_GPReadEnable.load(std::memory_order_relaxed);
|
|
|
|
|
m_cp_status_reg.UnderflowLoWatermark = fifo.bFF_LoWatermark.load(std::memory_order_relaxed);
|
|
|
|
|
m_cp_status_reg.OverflowHiWatermark = fifo.bFF_HiWatermark.load(std::memory_order_relaxed);
|
|
|
|
|
m_cp_status_reg.Breakpoint = m_fifo.bFF_Breakpoint.load(std::memory_order_relaxed);
|
|
|
|
|
m_cp_status_reg.ReadIdle = !m_fifo.CPReadWriteDistance.load(std::memory_order_relaxed) ||
|
|
|
|
|
(m_fifo.CPReadPointer.load(std::memory_order_relaxed) ==
|
|
|
|
|
m_fifo.CPWritePointer.load(std::memory_order_relaxed));
|
|
|
|
|
m_cp_status_reg.CommandIdle = !m_fifo.CPReadWriteDistance.load(std::memory_order_relaxed) ||
|
|
|
|
|
Fifo::AtBreakpoint(m_system) ||
|
|
|
|
|
!m_fifo.bFF_GPReadEnable.load(std::memory_order_relaxed);
|
|
|
|
|
m_cp_status_reg.UnderflowLoWatermark = m_fifo.bFF_LoWatermark.load(std::memory_order_relaxed);
|
|
|
|
|
m_cp_status_reg.OverflowHiWatermark = m_fifo.bFF_HiWatermark.load(std::memory_order_relaxed);
|
|
|
|
|
|
|
|
|
|
DEBUG_LOG_FMT(COMMANDPROCESSOR, "\t Read from STATUS_REGISTER : {:04x}", m_cp_status_reg.Hex);
|
|
|
|
|
DEBUG_LOG_FMT(COMMANDPROCESSOR,
|
|
|
|
@ -603,30 +600,28 @@ void CommandProcessorManager::SetCpStatusRegister(Core::System& system)
|
|
|
|
|
m_cp_status_reg.UnderflowLoWatermark ? "ON" : "OFF");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void CommandProcessorManager::SetCpControlRegister(Core::System& system)
|
|
|
|
|
void CommandProcessorManager::SetCpControlRegister()
|
|
|
|
|
{
|
|
|
|
|
auto& fifo = m_fifo;
|
|
|
|
|
m_fifo.bFF_BPInt.store(m_cp_ctrl_reg.BPInt, std::memory_order_relaxed);
|
|
|
|
|
m_fifo.bFF_BPEnable.store(m_cp_ctrl_reg.BPEnable, std::memory_order_relaxed);
|
|
|
|
|
m_fifo.bFF_HiWatermarkInt.store(m_cp_ctrl_reg.FifoOverflowIntEnable, std::memory_order_relaxed);
|
|
|
|
|
m_fifo.bFF_LoWatermarkInt.store(m_cp_ctrl_reg.FifoUnderflowIntEnable, std::memory_order_relaxed);
|
|
|
|
|
m_fifo.bFF_GPLinkEnable.store(m_cp_ctrl_reg.GPLinkEnable, std::memory_order_relaxed);
|
|
|
|
|
|
|
|
|
|
fifo.bFF_BPInt.store(m_cp_ctrl_reg.BPInt, std::memory_order_relaxed);
|
|
|
|
|
fifo.bFF_BPEnable.store(m_cp_ctrl_reg.BPEnable, std::memory_order_relaxed);
|
|
|
|
|
fifo.bFF_HiWatermarkInt.store(m_cp_ctrl_reg.FifoOverflowIntEnable, std::memory_order_relaxed);
|
|
|
|
|
fifo.bFF_LoWatermarkInt.store(m_cp_ctrl_reg.FifoUnderflowIntEnable, std::memory_order_relaxed);
|
|
|
|
|
fifo.bFF_GPLinkEnable.store(m_cp_ctrl_reg.GPLinkEnable, std::memory_order_relaxed);
|
|
|
|
|
|
|
|
|
|
if (fifo.bFF_GPReadEnable.load(std::memory_order_relaxed) && !m_cp_ctrl_reg.GPReadEnable)
|
|
|
|
|
if (m_fifo.bFF_GPReadEnable.load(std::memory_order_relaxed) && !m_cp_ctrl_reg.GPReadEnable)
|
|
|
|
|
{
|
|
|
|
|
fifo.bFF_GPReadEnable.store(m_cp_ctrl_reg.GPReadEnable, std::memory_order_relaxed);
|
|
|
|
|
system.GetFifo().FlushGpu();
|
|
|
|
|
m_fifo.bFF_GPReadEnable.store(m_cp_ctrl_reg.GPReadEnable, std::memory_order_relaxed);
|
|
|
|
|
m_system.GetFifo().FlushGpu();
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
fifo.bFF_GPReadEnable = m_cp_ctrl_reg.GPReadEnable;
|
|
|
|
|
m_fifo.bFF_GPReadEnable = m_cp_ctrl_reg.GPReadEnable;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DEBUG_LOG_FMT(COMMANDPROCESSOR, "\t GPREAD {} | BP {} | Int {} | OvF {} | UndF {} | LINK {}",
|
|
|
|
|
fifo.bFF_GPReadEnable.load(std::memory_order_relaxed) ? "ON" : "OFF",
|
|
|
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|
fifo.bFF_BPEnable.load(std::memory_order_relaxed) ? "ON" : "OFF",
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fifo.bFF_BPInt.load(std::memory_order_relaxed) ? "ON" : "OFF",
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m_fifo.bFF_GPReadEnable.load(std::memory_order_relaxed) ? "ON" : "OFF",
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m_fifo.bFF_BPEnable.load(std::memory_order_relaxed) ? "ON" : "OFF",
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m_fifo.bFF_BPInt.load(std::memory_order_relaxed) ? "ON" : "OFF",
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m_cp_ctrl_reg.FifoOverflowIntEnable ? "ON" : "OFF",
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m_cp_ctrl_reg.FifoUnderflowIntEnable ? "ON" : "OFF",
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m_cp_ctrl_reg.GPLinkEnable ? "ON" : "OFF");
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@ -638,11 +633,8 @@ void CommandProcessorManager::SetCpClearRegister()
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{
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}
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void CommandProcessorManager::HandleUnknownOpcode(Core::System& system, u8 cmd_byte,
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const u8* buffer, bool preprocess)
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void CommandProcessorManager::HandleUnknownOpcode(u8 cmd_byte, const u8* buffer, bool preprocess)
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{
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const auto& fifo = m_fifo;
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// Datel software uses 0x01 during startup, and Mario Party 5's Wiggler capsule accidentally uses
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// 0x01-0x03 due to sending 4 more vertices than intended (see https://dolp.in/i8104).
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// Prince of Persia: Rival Swords sends 0x3f if the home menu is opened during the intro cutscene
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@ -667,7 +659,7 @@ void CommandProcessorManager::HandleUnknownOpcode(Core::System& system, u8 cmd_b
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// PC and LR are meaningless when using the fifoplayer, and will generally not be helpful if the
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// unknown opcode is inside of a display list. Also note that the changes in GPFifo.h are not
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// accurate and may introduce timing issues.
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const auto& ppc_state = system.GetPPCState();
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const auto& ppc_state = m_system.GetPPCState();
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GENERIC_LOG_FMT(
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Common::Log::LogType::VIDEO, log_level,
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"FIFO: Unknown Opcode {:#04x} @ {}, preprocessing = {}, CPBase: {:#010x}, CPEnd: "
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@ -677,19 +669,19 @@ void CommandProcessorManager::HandleUnknownOpcode(Core::System& system, u8 cmd_b
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"{}, bFF_GPLinkEnable: {}, bFF_HiWatermarkInt: {}, bFF_LoWatermarkInt: {}, "
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"approximate PC: {:08x}, approximate LR: {:08x}",
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cmd_byte, fmt::ptr(buffer), preprocess ? "yes" : "no",
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fifo.CPBase.load(std::memory_order_relaxed), fifo.CPEnd.load(std::memory_order_relaxed),
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fifo.CPHiWatermark, fifo.CPLoWatermark,
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fifo.CPReadWriteDistance.load(std::memory_order_relaxed),
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fifo.CPWritePointer.load(std::memory_order_relaxed),
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fifo.CPReadPointer.load(std::memory_order_relaxed),
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fifo.CPBreakpoint.load(std::memory_order_relaxed),
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fifo.bFF_GPReadEnable.load(std::memory_order_relaxed) ? "true" : "false",
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fifo.bFF_BPEnable.load(std::memory_order_relaxed) ? "true" : "false",
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fifo.bFF_BPInt.load(std::memory_order_relaxed) ? "true" : "false",
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fifo.bFF_Breakpoint.load(std::memory_order_relaxed) ? "true" : "false",
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fifo.bFF_GPLinkEnable.load(std::memory_order_relaxed) ? "true" : "false",
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fifo.bFF_HiWatermarkInt.load(std::memory_order_relaxed) ? "true" : "false",
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fifo.bFF_LoWatermarkInt.load(std::memory_order_relaxed) ? "true" : "false", ppc_state.pc,
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m_fifo.CPBase.load(std::memory_order_relaxed), m_fifo.CPEnd.load(std::memory_order_relaxed),
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m_fifo.CPHiWatermark, m_fifo.CPLoWatermark,
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m_fifo.CPReadWriteDistance.load(std::memory_order_relaxed),
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m_fifo.CPWritePointer.load(std::memory_order_relaxed),
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m_fifo.CPReadPointer.load(std::memory_order_relaxed),
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m_fifo.CPBreakpoint.load(std::memory_order_relaxed),
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m_fifo.bFF_GPReadEnable.load(std::memory_order_relaxed) ? "true" : "false",
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m_fifo.bFF_BPEnable.load(std::memory_order_relaxed) ? "true" : "false",
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m_fifo.bFF_BPInt.load(std::memory_order_relaxed) ? "true" : "false",
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m_fifo.bFF_Breakpoint.load(std::memory_order_relaxed) ? "true" : "false",
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m_fifo.bFF_GPLinkEnable.load(std::memory_order_relaxed) ? "true" : "false",
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m_fifo.bFF_HiWatermarkInt.load(std::memory_order_relaxed) ? "true" : "false",
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m_fifo.bFF_LoWatermarkInt.load(std::memory_order_relaxed) ? "true" : "false", ppc_state.pc,
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LR(ppc_state));
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if (!m_is_fifo_error_seen && !suppress_panic_alert)
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@ -699,9 +691,9 @@ void CommandProcessorManager::HandleUnknownOpcode(Core::System& system, u8 cmd_b
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// The panic alert contains an explanatory part that's worded differently depending on the
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// user's settings, so as to offer the most relevant advice to the user.
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const char* advice;
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if (IsOnThread(system) && !system.GetFifo().UseDeterministicGPUThread())
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if (IsOnThread(m_system) && !m_system.GetFifo().UseDeterministicGPUThread())
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{
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if (!system.GetCoreTiming().UseSyncOnSkipIdle() && !system.GetFifo().UseSyncGPU())
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if (!m_system.GetCoreTiming().UseSyncOnSkipIdle() && !m_system.GetFifo().UseSyncGPU())
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{
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// The SyncOnSkipIdle setting is only in the Android GUI, so we use the INI name on other platforms.
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//
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