From 8cfceb1186c80a4ad94618cfa8d8aa942134247e Mon Sep 17 00:00:00 2001 From: Pierre Bourdon Date: Tue, 8 Jan 2013 00:00:30 +0100 Subject: [PATCH] Disable swapping cmp with instructions potentially raising interrupts Workaround for issue 5864 disabling parts of an optimization in the JIT. This is not the best solution to fix this issue, but at least it does not crash. --- Source/Core/Core/Src/PowerPC/PPCAnalyst.cpp | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/Source/Core/Core/Src/PowerPC/PPCAnalyst.cpp b/Source/Core/Core/Src/PowerPC/PPCAnalyst.cpp index ddfec1c328..fa9f278c29 100644 --- a/Source/Core/Core/Src/PowerPC/PPCAnalyst.cpp +++ b/Source/Core/Core/Src/PowerPC/PPCAnalyst.cpp @@ -246,17 +246,13 @@ bool CanSwapAdjacentOps(const CodeOp &a, const CodeOp &b) return false; } - // For now, only integer ops acceptable. - switch (b_info->type) { - case OPTYPE_INTEGER: - case OPTYPE_LOAD: - case OPTYPE_STORE: - //case OPTYPE_LOADFP: - //case OPTYPE_STOREFP: - break; - default: + // For now, only integer ops acceptable. Any instruction which can raise an + // interrupt is *not* a possible swap candidate: see [1] for an example of + // a crash caused by this error. + // + // [1] https://code.google.com/p/dolphin-emu/issues/detail?id=5864#c7 + if (b_info->type != OPTYPE_INTEGER) return false; - } // Check that we have no register collisions. // That is, check that none of b's outputs matches any of a's inputs,