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JitArm64: Implement mffsx 

Part 2 of implementing the FPSCR system register instructions.
This commit is contained in:
JosJuice 2021-06-24 11:47:42 +02:00
parent c77a5f7e32
commit 8cd37e040a
3 changed files with 34 additions and 1 deletions
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1
Source/Core/Core/PowerPC/JitArm64/Jit.h
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@ -119,6 +119,7 @@ public:
void mfcr(UGeckoInstruction inst);
void mtcrf(UGeckoInstruction inst);
void mcrfs(UGeckoInstruction inst);
void mffsx(UGeckoInstruction inst);
// LoadStore
void lXX(UGeckoInstruction inst);

32
Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp
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@ -721,3 +721,35 @@ void JitArm64::mcrfs(UGeckoInstruction inst)
gpr.Unlock(WA);
}
void JitArm64::mffsx(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITSystemRegistersOff);
FALLBACK_IF(inst.Rc);
ARM64Reg WA = gpr.GetReg();
ARM64Reg XA = EncodeRegTo64(WA);
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
ARM64Reg VD = fpr.RW(inst.FD, RegType::LowerPair);
ARM64Reg WB = gpr.GetReg();
// FPSCR.FEX = 0;
// FPSCR.VX = (FPSCR.Hex & FPSCR_VX_ANY) != 0;
// (FEX is right next to VX, so we can set both using one BFI instruction)
MOVI2R(WB, FPSCR_VX_ANY);
TST(WA, WB);
CSET(WB, CCFlags::CC_NEQ);
BFI(WA, WB, 31 - 2, 2);
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
// Vd = FPSCR.Hex | 0xFFF8'0000'0000'0000;
ORR(XA, XA, 13, 12, true);
m_float_emit.FMOV(EncodeRegToDouble(VD), XA);
gpr.Unlock(WA);
gpr.Unlock(WB);
}

2
Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
View File

@ -316,7 +316,7 @@ constexpr std::array<GekkoOPTemplate, 15> table63{{
{12, &JitArm64::frspx}, // frspx
{64, &JitArm64::mcrfs}, // mcrfs
{583, &JitArm64::FallBackToInterpreter}, // mffsx
{583, &JitArm64::mffsx}, // mffsx
{70, &JitArm64::FallBackToInterpreter}, // mtfsb0x
{38, &JitArm64::FallBackToInterpreter}, // mtfsb1x
{134, &JitArm64::FallBackToInterpreter}, // mtfsfix