Merge pull request #2555 from Sonicadvance1/aarch64_rebase_ppsspp_emitter
[AArch64] Upstream PPSSPP's emitter changes.
This commit is contained in:
Ryan Houdek
commit
8c2e5e2860
File diff suppressed because it is too large
Load Diff
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@ -1,4 +1,4 @@
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// Copyright 2014 Dolphin Emulator Project
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// Copyright 2015 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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@ -74,19 +74,34 @@ enum ARM64Reg
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PLTL2KEEP, PLTL2STRM,
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PLTL3KEEP, PLTL3STRM,
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WZR = WSP,
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ZR = SP,
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INVALID_REG = 0xFFFFFFFF
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};
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inline bool Is64Bit(ARM64Reg reg) { return reg & 0x20; }
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inline bool Is64Bit(ARM64Reg reg) { return (reg & 0x20) != 0; }
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inline bool IsSingle(ARM64Reg reg) { return (reg & 0xC0) == 0x40; }
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inline bool IsDouble(ARM64Reg reg) { return (reg & 0xC0) == 0x80; }
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inline bool IsScalar(ARM64Reg reg) { return IsSingle(reg) || IsDouble(reg); }
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inline bool IsQuad(ARM64Reg reg) { return (reg & 0xC0) == 0xC0; }
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inline bool IsVector(ARM64Reg reg) { return (reg & 0xC0) != 0; }
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inline bool IsGPR(ARM64Reg reg) { return (int)reg < 0x40; }
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inline ARM64Reg DecodeReg(ARM64Reg reg) { return (ARM64Reg)(reg & 0x1F); }
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inline ARM64Reg EncodeRegTo64(ARM64Reg reg) { return (ARM64Reg)(reg | 0x20); }
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inline ARM64Reg EncodeRegToSingle(ARM64Reg reg) { return (ARM64Reg)(DecodeReg(reg) + S0); }
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inline ARM64Reg EncodeRegToDouble(ARM64Reg reg) { return (ARM64Reg)((reg & ~0xC0) | 0x80); }
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inline ARM64Reg EncodeRegToQuad(ARM64Reg reg) { return (ARM64Reg)(reg | 0xC0); }
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// For AND/TST/ORR/EOR etc
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bool IsImmLogical(uint64_t value, unsigned int width, unsigned int *n, unsigned int *imm_s, unsigned int *imm_r);
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// For ADD/SUB
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bool IsImmArithmetic(uint64_t input, u32 *val, bool *shift);
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float FPImm8ToFloat(uint8_t bits);
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bool FPImm8FromFloat(float value, uint8_t *immOut);
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enum OpType
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{
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TYPE_IMM = 0,
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@ -109,8 +124,7 @@ enum IndexType
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INDEX_UNSIGNED,
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INDEX_POST,
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INDEX_PRE,
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// Only for VFP loadstore paired
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INDEX_SIGNED,
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INDEX_SIGNED, // used in LDP/STP
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};
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enum ShiftAmount
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@ -121,12 +135,12 @@ enum ShiftAmount
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SHIFT_48 = 3,
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};
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enum ExtendType
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{
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EXTEND_UXTW = 2,
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EXTEND_LSL = 3, // Default for zero shift amount
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EXTEND_SXTW = 6,
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EXTEND_SXTX = 7,
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enum RoundingMode {
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ROUND_A, // round to nearest, ties to away
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ROUND_M, // round towards -inf
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ROUND_N, // round to nearest, ties to even
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ROUND_P, // round towards +inf
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ROUND_Z, // round towards zero
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};
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struct FixupBranch
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@ -157,6 +171,9 @@ enum PStateField
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FIELD_SPSel = 0,
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FIELD_DAIFSet,
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FIELD_DAIFClr,
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FIELD_NZCV, // The only system registers accessible from EL0 (user space)
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FIELD_FPCR = 0x340,
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FIELD_FPSR = 0x341,
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};
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enum SystemHint
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@ -252,6 +269,7 @@ public:
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m_width = WIDTH_32BIT;
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m_extend = EXTEND_UXTW;
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}
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m_shifttype = ST_LSL;
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}
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ArithOption(ARM64Reg Rd, ShiftType shift_type, u32 shift)
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{
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@ -333,7 +351,7 @@ private:
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void EncodeBitfieldMOVInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
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void EncodeLoadStoreRegisterOffset(u32 size, u32 opc, ARM64Reg Rt, ARM64Reg Rn, ArithOption Rm);
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void EncodeAddSubImmInst(u32 op, bool flags, u32 shift, u32 imm, ARM64Reg Rn, ARM64Reg Rd);
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void EncodeLogicalImmInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
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void EncodeLogicalImmInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, int n);
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void EncodeLoadStorePair(u32 op, u32 load, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
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void EncodeAddressInst(u32 op, ARM64Reg Rd, s32 imm);
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void EncodeLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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@ -398,7 +416,7 @@ public:
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// Unconditional Branch (register)
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void BR(ARM64Reg Rn);
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void BLR(ARM64Reg Rn);
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void RET(ARM64Reg Rn);
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void RET(ARM64Reg Rn = X30);
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void ERET();
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void DRPS();
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@ -414,6 +432,10 @@ public:
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// System
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void _MSR(PStateField field, u8 imm);
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void _MSR(PStateField field, ARM64Reg Rt);
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void MRS(ARM64Reg Rt, PStateField field);
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void HINT(SystemHint op);
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void CLREX();
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void DSB(BarrierType type);
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@ -454,6 +476,17 @@ public:
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void CSINV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, CCFlags cond);
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void CSNEG(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, CCFlags cond);
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// Aliases
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void CSET(ARM64Reg Rd, CCFlags cond)
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{
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ARM64Reg zr = Is64Bit(Rd) ? ZR : WZR;
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CSINC(Rd, zr, zr, (CCFlags)((u32)cond ^ 1));
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}
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void NEG(ARM64Reg Rd, ARM64Reg Rs)
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{
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SUB(Rd, Is64Bit(Rd) ? ZR : WZR, Rs);
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}
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// Data-Processing 1 source
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void RBIT(ARM64Reg Rd, ARM64Reg Rn);
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void REV16(ARM64Reg Rd, ARM64Reg Rn);
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@ -500,15 +533,34 @@ public:
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void EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
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void ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
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void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
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// Wrap the above for saner syntax
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void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { AND(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
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void BIC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { BIC(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
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void ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ORR(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
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void ORN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ORN(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
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void EOR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { EOR(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
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void EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { EON(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
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void ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ANDS(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
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void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { BICS(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
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// Convenience wrappers around ORR. These match the official convenience syntax.
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void MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift);
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void MOV(ARM64Reg Rd, ARM64Reg Rm);
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void MVN(ARM64Reg Rd, ARM64Reg Rm);
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// TODO: These are "slow" as they use arith+shift, should be replaced with UBFM/EXTR variants.
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void LSR(ARM64Reg Rd, ARM64Reg Rm, int shift);
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void LSL(ARM64Reg Rd, ARM64Reg Rm, int shift);
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void ASR(ARM64Reg Rd, ARM64Reg Rm, int shift);
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void ROR(ARM64Reg Rd, ARM64Reg Rm, int shift);
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// Logical (immediate)
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void AND(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
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void ANDS(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
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void EOR(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
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void ORR(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
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void TST(ARM64Reg Rn, u32 immr, u32 imms);
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void AND(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);
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void ANDS(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);
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void EOR(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);
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void ORR(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);
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void TST(ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);
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// Add/subtract (immediate)
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void ADD(ARM64Reg Rd, ARM64Reg Rn, u32 imm, bool shift = false);
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@ -526,12 +578,22 @@ public:
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void BFM(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
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void SBFM(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
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void UBFM(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms);
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// Extract register (ROR with two inputs, if same then faster on A67)
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void EXTR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u32 shift);
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// Aliases
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void SXTB(ARM64Reg Rd, ARM64Reg Rn);
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void SXTH(ARM64Reg Rd, ARM64Reg Rn);
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void SXTW(ARM64Reg Rd, ARM64Reg Rn);
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void UXTB(ARM64Reg Rd, ARM64Reg Rn);
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void UXTH(ARM64Reg Rd, ARM64Reg Rn);
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void UBFX(ARM64Reg Rd, ARM64Reg Rn, int lsb, int width)
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{
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UBFM(Rd, Rn, lsb, lsb + width <= (Is64Bit(Rn) ? 64 : 32));
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}
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// Load Register (Literal)
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void LDR(ARM64Reg Rt, u32 imm);
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void LDRSW(ARM64Reg Rt, u32 imm);
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@ -610,6 +672,32 @@ public:
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// Wrapper around MOVZ+MOVK
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void MOVI2R(ARM64Reg Rd, u64 imm, bool optimize = true);
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template <class P>
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void MOVP2R(ARM64Reg Rd, P *ptr)
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{
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_assert_msg_(DYNA_REC, Is64Bit(Rd), "Can't store pointers in 32-bit registers");
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MOVI2R(Rd, (uintptr_t)ptr);
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}
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// Wrapper around AND x, y, imm etc. If you are sure the imm will work, no need to pass a scratch register.
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void ANDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void ANDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void TSTI2R(ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG) { ANDSI2R(Is64Bit(Rn) ? ZR : WZR, Rn, imm, scratch); }
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void ORRI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void EORI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void CMPI2R(ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void ADDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void SUBI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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void SUBSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch = INVALID_REG);
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bool TryADDI2R(ARM64Reg Rd, ARM64Reg Rn, u32 imm);
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bool TrySUBI2R(ARM64Reg Rd, ARM64Reg Rn, u32 imm);
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bool TryCMPI2R(ARM64Reg Rn, u32 imm);
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bool TryANDI2R(ARM64Reg Rd, ARM64Reg Rn, u32 imm);
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bool TryORRI2R(ARM64Reg Rd, ARM64Reg Rn, u32 imm);
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bool TryEORI2R(ARM64Reg Rd, ARM64Reg Rn, u32 imm);
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// ABI related
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void ABI_PushRegisters(BitSet32 registers);
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@ -633,10 +721,17 @@ public:
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ARM64Reg ABI_SetupLambda(const std::function<T(Args...)>* f)
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{
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auto trampoline = &ARM64XEmitter::CallLambdaTrampoline<T, Args...>;
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MOVI2R(X30, (u64)trampoline);
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MOVI2R(X0, (u64)const_cast<void*>((const void*)f));
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MOVI2R(X30, (uintptr_t)trampoline);
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MOVI2R(X0, (uintptr_t)const_cast<void*>((const void*)f));
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return X30;
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}
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// Plain function call
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void QuickCallFunction(ARM64Reg scratchreg, const void *func);
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template <typename T> void QuickCallFunction(ARM64Reg scratchreg, T func)
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{
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QuickCallFunction(scratchreg, (const void *)func);
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}
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};
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class ARM64FloatEmitter
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@ -671,14 +766,28 @@ public:
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// Scalar - 1 Source
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void FABS(ARM64Reg Rd, ARM64Reg Rn);
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void FNEG(ARM64Reg Rd, ARM64Reg Rn);
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void FSQRT(ARM64Reg Rd, ARM64Reg Rn);
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void FMOV(ARM64Reg Rd, ARM64Reg Rn, bool top = false); // Also generalized move between GPR/FP
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// Scalar - 2 Source
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void FADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMUL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FSUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FDIV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMAX(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMIN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMAXNM(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMINNM(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FNMUL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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// Scalar - 3 Source. Note - the accumulator is last on ARM!
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void FMADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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void FMSUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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void FNMADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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void FNMSUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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// Scalar floating point immediate
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void FMOV(ARM64Reg Rd, u32 imm);
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void FMOV(ARM64Reg Rd, uint8_t imm8);
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// Vector
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void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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@ -686,7 +795,10 @@ public:
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void DUP(u8 size, ARM64Reg Rd, ARM64Reg Rn, u8 index);
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void FABS(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FADD(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMLA(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FMLS(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void FCVTL(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FCVTL2(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FCVTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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void FCVTZS(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void FCVTZU(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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@ -697,11 +809,17 @@ public:
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void FSUB(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void NOT(ARM64Reg Rd, ARM64Reg Rn);
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void ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void MOV(ARM64Reg Rd, ARM64Reg Rn)
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{
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ORR(Rd, Rn, Rn);
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}
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void REV16(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void REV32(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void REV64(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void SCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn);
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void SCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale);
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void UCVTF(u8 size, ARM64Reg Rd, ARM64Reg Rn, int scale);
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void XTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
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// Move
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@ -714,11 +832,20 @@ public:
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// One source
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void FCVT(u8 size_to, u8 size_from, ARM64Reg Rd, ARM64Reg Rn);
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// Conversion between float and integer
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void FMOV(u8 size, bool top, ARM64Reg Rd, ARM64Reg Rn);
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// Scalar convert float to int, in a lot of variants.
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// Note that the scalar version of this operation has two encodings, one that goes to an integer register
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// and one that outputs to a scalar fp register.
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void FCVTS(ARM64Reg Rd, ARM64Reg Rn, RoundingMode round);
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void FCVTU(ARM64Reg Rd, ARM64Reg Rn, RoundingMode round);
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// Scalar convert int to float. No rounding mode specifier necessary.
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void SCVTF(ARM64Reg Rd, ARM64Reg Rn);
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void UCVTF(ARM64Reg Rd, ARM64Reg Rn);
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// Scalar fixed point to float. scale is the number of fractional bits.
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void SCVTF(ARM64Reg Rd, ARM64Reg Rn, int scale);
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void UCVTF(ARM64Reg Rd, ARM64Reg Rn, int scale);
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// Float comparison
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void FCMP(ARM64Reg Rn, ARM64Reg Rm);
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void FCMP(ARM64Reg Rn);
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@ -746,13 +873,22 @@ public:
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// Shift by immediate
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void SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
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void SSHLL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
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void USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
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void USHLL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
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void SHRN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
|
||||
void SHRN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift);
|
||||
void SXTL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void SXTL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void UXTL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void UXTL2(u8 src_size, ARM64Reg Rd, ARM64Reg Rn);
|
||||
|
||||
// vector x indexed element
|
||||
void FMUL(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u8 index);
|
||||
void FMLA(u8 esize, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u8 index);
|
||||
|
||||
void MOVI2F(ARM64Reg Rd, float value, ARM64Reg scratch = INVALID_REG, bool negate = false);
|
||||
void MOVI2FDUP(ARM64Reg Rd, float value, ARM64Reg scratch = INVALID_REG);
|
||||
|
||||
// ABI related
|
||||
void ABI_PushRegisters(BitSet32 registers, ARM64Reg tmp = INVALID_REG);
|
||||
|
|
@ -764,25 +900,35 @@ private:
|
|||
|
||||
// Emitting functions
|
||||
void EmitLoadStoreImmediate(u8 size, u32 opc, IndexType type, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
||||
void Emit2Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
||||
void EmitScalar2Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
||||
void EmitThreeSame(bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
||||
void EmitCopy(bool Q, u32 op, u32 imm5, u32 imm4, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void Emit2RegMisc(bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void Emit2RegMisc(bool Q, bool U, u32 size, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void EmitLoadStoreSingleStructure(bool L, bool R, u32 opcode, bool S, u32 size, ARM64Reg Rt, ARM64Reg Rn);
|
||||
void EmitLoadStoreSingleStructure(bool L, bool R, u32 opcode, bool S, u32 size, ARM64Reg Rt, ARM64Reg Rn, ARM64Reg Rm);
|
||||
void Emit1Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void EmitConversion(bool sf, bool S, u32 type, u32 rmode, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void EmitConversion2(bool sf, bool S, bool direction, u32 type, u32 rmode, u32 opcode, int scale, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void EmitCompare(bool M, bool S, u32 op, u32 opcode2, ARM64Reg Rn, ARM64Reg Rm);
|
||||
void EmitCondSelect(bool M, bool S, CCFlags cond, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
||||
void EmitPermute(u32 size, u32 op, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
||||
void EmitScalarImm(bool M, bool S, u32 type, u32 imm5, ARM64Reg Rd, u32 imm);
|
||||
void EmitShiftImm(bool U, u32 immh, u32 immb, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void EmitScalarImm(bool M, bool S, u32 type, u32 imm5, ARM64Reg Rd, u32 imm8);
|
||||
void EmitShiftImm(bool Q, bool U, u32 immh, u32 immb, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void EmitScalarShiftImm(bool U, u32 immh, u32 immb, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void EmitLoadStoreMultipleStructure(u32 size, bool L, u32 opcode, ARM64Reg Rt, ARM64Reg Rn);
|
||||
void EmitLoadStoreMultipleStructurePost(u32 size, bool L, u32 opcode, ARM64Reg Rt, ARM64Reg Rn, ARM64Reg Rm);
|
||||
void EmitScalar1Source(bool M, bool S, u32 type, u32 opcode, ARM64Reg Rd, ARM64Reg Rn);
|
||||
void EmitVectorxElement(bool U, u32 size, bool L, u32 opcode, bool H, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
|
||||
void EmitLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
|
||||
void EmitConvertScalarToInt(ARM64Reg Rd, ARM64Reg Rn, RoundingMode round, bool sign);
|
||||
void EmitScalar3Source(bool isDouble, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra, int opcode);
|
||||
void EncodeLoadStorePair(u32 size, bool load, IndexType type, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, s32 imm);
|
||||
|
||||
void SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper);
|
||||
void USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper);
|
||||
void SHRN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper);
|
||||
void SXTL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, bool upper);
|
||||
void UXTL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, bool upper);
|
||||
};
|
||||
|
||||
class ARM64CodeBlock : public CodeBlock<ARM64XEmitter>
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ void JitArm64::psq_l(UGeckoInstruction inst)
|
|||
|
||||
fpr.BindToRegister(inst.RS, false);
|
||||
ARM64Reg VS = fpr.R(inst.RS);
|
||||
m_float_emit.FCVTL(64, EncodeRegToDouble(VS), D0);
|
||||
m_float_emit.FCVTL(64, VS, D0);
|
||||
if (inst.W)
|
||||
{
|
||||
m_float_emit.FMOV(D0, 0x70); // 1.0 as a Double
|
||||
|
|
|
|||
Loading…
Reference in New Issue