ShuriZma
/
dolphin
mirror of https://github.com/dolphin-emu/dolphin.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #11242 from Sintendo/arm64cmp 

JitArm64: Optimize cmp
This commit is contained in:
Admiral H. Curtiss 2022-11-04 23:13:09 +01:00 committed by GitHub
parent c2e6d85ba7 d0de68c41b
commit 8b4e315fb7
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 48 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
Source/Core/Common/Arm64Emitter.h
View File

@ -309,6 +309,18 @@ enum class ShiftType
ROR = 3, ROR = 3,
}; };
enum class ExtendSpecifier
{
UXTB = 0x0,
UXTH = 0x1,
UXTW = 0x2, /* Also LSL on 32bit width */
UXTX = 0x3, /* Also LSL on 64bit width */
SXTB = 0x4,
SXTH = 0x5,
SXTW = 0x6,
SXTX = 0x7,
};
enum class IndexType enum class IndexType
{ {
Unsigned, Unsigned,
@ -405,18 +417,6 @@ private:
Width64Bit, Width64Bit,
}; };
enum class ExtendSpecifier
{
UXTB = 0x0,
UXTH = 0x1,
UXTW = 0x2, /* Also LSL on 32bit width */
UXTX = 0x3, /* Also LSL on 64bit width */
SXTB = 0x4,
SXTH = 0x5,
SXTW = 0x6,
SXTX = 0x7,
};
enum class TypeSpecifier enum class TypeSpecifier
{ {
ExtendedReg, ExtendedReg,
@ -463,6 +463,15 @@ public:
} }
m_shifttype = ShiftType::LSL; m_shifttype = ShiftType::LSL;
} }
ArithOption(ARM64Reg Rd, ExtendSpecifier extend_type, u32 shift = 0)
{
m_destReg = Rd;
m_width = Is64Bit(Rd) ? WidthSpecifier::Width64Bit : WidthSpecifier::Width32Bit;
m_extend = extend_type;
m_type = TypeSpecifier::ExtendedReg;
m_shifttype = ShiftType::LSL;
m_shift = shift;
}
ArithOption(ARM64Reg Rd, ShiftType shift_type, u32 shift) ArithOption(ARM64Reg Rd, ShiftType shift_type, u32 shift)
{ {
m_destReg = Rd; m_destReg = Rd;

43
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
View File

@ -578,25 +578,29 @@ void JitArm64::cmp(UGeckoInstruction inst)
s64 A = static_cast<s32>(gpr.GetImm(a)); s64 A = static_cast<s32>(gpr.GetImm(a));
s64 B = static_cast<s32>(gpr.GetImm(b)); s64 B = static_cast<s32>(gpr.GetImm(b));
MOVI2R(CR, A - B); MOVI2R(CR, A - B);
return;
} }
else if (gpr.IsImm(a) && !gpr.GetImm(a))
if (gpr.IsImm(b) && !gpr.GetImm(b)) {
NEG(EncodeRegTo32(CR), gpr.R(b));
SXTW(CR, EncodeRegTo32(CR));
}
else if (gpr.IsImm(a) && gpr.GetImm(a) == 0xFFFFFFFF)
{
MVN(EncodeRegTo32(CR), gpr.R(b));
SXTW(CR, EncodeRegTo32(CR));
}
else if (gpr.IsImm(b) && !gpr.GetImm(b))
{ {
SXTW(CR, gpr.R(a)); SXTW(CR, gpr.R(a));
return;
} }
else
ARM64Reg WA = gpr.GetReg(); {
ARM64Reg XA = EncodeRegTo64(WA);
ARM64Reg RA = gpr.R(a); ARM64Reg RA = gpr.R(a);
ARM64Reg RB = gpr.R(b); ARM64Reg RB = gpr.R(b);
SXTW(XA, RA); SXTW(CR, RA);
SXTW(CR, RB); SUB(CR, CR, RB, ArithOption(RB, ExtendSpecifier::SXTW));
SUB(CR, XA, CR); }
gpr.Unlock(WA);
} }
void JitArm64::cmpl(UGeckoInstruction inst) void JitArm64::cmpl(UGeckoInstruction inst)
@ -615,16 +619,19 @@ void JitArm64::cmpl(UGeckoInstruction inst)
u64 A = gpr.GetImm(a); u64 A = gpr.GetImm(a);
u64 B = gpr.GetImm(b); u64 B = gpr.GetImm(b);
MOVI2R(CR, A - B); MOVI2R(CR, A - B);
return;
} }
else if (gpr.IsImm(a) && !gpr.GetImm(a))
if (gpr.IsImm(b) && !gpr.GetImm(b)) {
NEG(CR, EncodeRegTo64(gpr.R(b)));
}
else if (gpr.IsImm(b) && !gpr.GetImm(b))
{ {
MOV(EncodeRegTo32(CR), gpr.R(a)); MOV(EncodeRegTo32(CR), gpr.R(a));
return;
} }
else
SUB(gpr.CR(crf), EncodeRegTo64(gpr.R(a)), EncodeRegTo64(gpr.R(b))); {
SUB(CR, EncodeRegTo64(gpr.R(a)), EncodeRegTo64(gpr.R(b)));
}
} }
void JitArm64::cmpi(UGeckoInstruction inst) void JitArm64::cmpi(UGeckoInstruction inst)