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Merge pull request #11242 from Sintendo/arm64cmp 

JitArm64: Optimize cmp
This commit is contained in:
Admiral H. Curtiss 2022-11-04 23:13:09 +01:00 committed by GitHub
parent c2e6d85ba7 d0de68c41b
commit 8b4e315fb7
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 48 additions and 32 deletions
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33
Source/Core/Common/Arm64Emitter.h
View File

@ -309,6 +309,18 @@ enum class ShiftType
ROR = 3,
};
enum class ExtendSpecifier
{
UXTB = 0x0,
UXTH = 0x1,
UXTW = 0x2, /* Also LSL on 32bit width */
UXTX = 0x3, /* Also LSL on 64bit width */
SXTB = 0x4,
SXTH = 0x5,
SXTW = 0x6,
SXTX = 0x7,
};
enum class IndexType
{
Unsigned,
@ -405,18 +417,6 @@ private:
Width64Bit,
};
enum class ExtendSpecifier
{
UXTB = 0x0,
UXTH = 0x1,
UXTW = 0x2, /* Also LSL on 32bit width */
UXTX = 0x3, /* Also LSL on 64bit width */
SXTB = 0x4,
SXTH = 0x5,
SXTW = 0x6,
SXTX = 0x7,
};
enum class TypeSpecifier
{
ExtendedReg,
@ -463,6 +463,15 @@ public:
}
m_shifttype = ShiftType::LSL;
}
ArithOption(ARM64Reg Rd, ExtendSpecifier extend_type, u32 shift = 0)
{
m_destReg = Rd;
m_width = Is64Bit(Rd) ? WidthSpecifier::Width64Bit : WidthSpecifier::Width32Bit;
m_extend = extend_type;
m_type = TypeSpecifier::ExtendedReg;
m_shifttype = ShiftType::LSL;
m_shift = shift;
}
ArithOption(ARM64Reg Rd, ShiftType shift_type, u32 shift)
{
m_destReg = Rd;

47
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
View File

@ -578,25 +578,29 @@ void JitArm64::cmp(UGeckoInstruction inst)
s64 A = static_cast<s32>(gpr.GetImm(a));
s64 B = static_cast<s32>(gpr.GetImm(b));
MOVI2R(CR, A - B);
return;
}
if (gpr.IsImm(b) && !gpr.GetImm(b))
else if (gpr.IsImm(a) && !gpr.GetImm(a))
{
NEG(EncodeRegTo32(CR), gpr.R(b));
SXTW(CR, EncodeRegTo32(CR));
}
else if (gpr.IsImm(a) && gpr.GetImm(a) == 0xFFFFFFFF)
{
MVN(EncodeRegTo32(CR), gpr.R(b));
SXTW(CR, EncodeRegTo32(CR));
}
else if (gpr.IsImm(b) && !gpr.GetImm(b))
{
SXTW(CR, gpr.R(a));
return;
}
else
{
ARM64Reg RA = gpr.R(a);
ARM64Reg RB = gpr.R(b);
ARM64Reg WA = gpr.GetReg();
ARM64Reg XA = EncodeRegTo64(WA);
ARM64Reg RA = gpr.R(a);
ARM64Reg RB = gpr.R(b);
SXTW(XA, RA);
SXTW(CR, RB);
SUB(CR, XA, CR);
gpr.Unlock(WA);
SXTW(CR, RA);
SUB(CR, CR, RB, ArithOption(RB, ExtendSpecifier::SXTW));
}
}
void JitArm64::cmpl(UGeckoInstruction inst)
@ -615,16 +619,19 @@ void JitArm64::cmpl(UGeckoInstruction inst)
u64 A = gpr.GetImm(a);
u64 B = gpr.GetImm(b);
MOVI2R(CR, A - B);
return;
}
if (gpr.IsImm(b) && !gpr.GetImm(b))
else if (gpr.IsImm(a) && !gpr.GetImm(a))
{
NEG(CR, EncodeRegTo64(gpr.R(b)));
}
else if (gpr.IsImm(b) && !gpr.GetImm(b))
{
MOV(EncodeRegTo32(CR), gpr.R(a));
return;
}
SUB(gpr.CR(crf), EncodeRegTo64(gpr.R(a)), EncodeRegTo64(gpr.R(b)));
else
{
SUB(CR, EncodeRegTo64(gpr.R(a)), EncodeRegTo64(gpr.R(b)));
}
}
void JitArm64::cmpi(UGeckoInstruction inst)