ShuriZma
/
dolphin
mirror of https://github.com/dolphin-emu/dolphin.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

JitArm64: Merge ps_sumX.

This commit is contained in:
degasus 2016-02-11 00:32:53 +01:00
parent 2d8e1bc34d
commit 8b32cd0738
3 changed files with 56 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Source/Core/Core/PowerPC/JitArm64/Jit.h
View File

@ -154,8 +154,7 @@ public:
void ps_nmsub(UGeckoInstruction inst); void ps_nmsub(UGeckoInstruction inst);
void ps_res(UGeckoInstruction inst); void ps_res(UGeckoInstruction inst);
void ps_sel(UGeckoInstruction inst); void ps_sel(UGeckoInstruction inst);
void ps_sum0(UGeckoInstruction inst); void ps_sumX(UGeckoInstruction inst);
void ps_sum1(UGeckoInstruction inst);
// Loadstore paired // Loadstore paired
void psq_l(UGeckoInstruction inst); void psq_l(UGeckoInstruction inst);

136
Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
View File

@ -17,53 +17,6 @@
using namespace Arm64Gen; using namespace Arm64Gen;
void JitArm64::ps_madd(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITPairedOff);
FALLBACK_IF(inst.Rc);
FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
ARM64Reg VA = fpr.R(a, REG_REG);
ARM64Reg VB = fpr.R(b, REG_REG);
ARM64Reg VC = fpr.R(c, REG_REG);
ARM64Reg VD = fpr.RW(d, REG_REG);
ARM64Reg V0 = fpr.GetReg();
m_float_emit.FMUL(64, V0, VA, VC);
m_float_emit.FADD(64, VD, V0, VB);
fpr.FixSinglePrecision(d);
fpr.Unlock(V0);
}
void JitArm64::ps_maddsX(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITPairedOff);
FALLBACK_IF(inst.Rc);
FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
bool upper = inst.SUBOP5 == 15;
ARM64Reg VA = fpr.R(a, REG_REG);
ARM64Reg VB = fpr.R(b, REG_REG);
ARM64Reg VC = fpr.R(c, REG_REG);
ARM64Reg VD = fpr.RW(d, REG_REG);
ARM64Reg V0 = fpr.GetReg();
m_float_emit.DUP(64, V0, VC, upper ? 1 : 0);
m_float_emit.FMUL(64, V0, V0, VA);
m_float_emit.FADD(64, VD, V0, VB);
fpr.FixSinglePrecision(d);
fpr.Unlock(V0);
}
void JitArm64::ps_mergeXX(UGeckoInstruction inst) void JitArm64::ps_mergeXX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
@ -130,6 +83,52 @@ void JitArm64::ps_mulsX(UGeckoInstruction inst)
fpr.FixSinglePrecision(d); fpr.FixSinglePrecision(d);
fpr.Unlock(V0); fpr.Unlock(V0);
} }
void JitArm64::ps_madd(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITPairedOff);
FALLBACK_IF(inst.Rc);
FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
ARM64Reg VA = fpr.R(a, REG_REG);
ARM64Reg VB = fpr.R(b, REG_REG);
ARM64Reg VC = fpr.R(c, REG_REG);
ARM64Reg VD = fpr.RW(d, REG_REG);
ARM64Reg V0 = fpr.GetReg();
m_float_emit.FMUL(64, V0, VA, VC);
m_float_emit.FADD(64, VD, V0, VB);
fpr.FixSinglePrecision(d);
fpr.Unlock(V0);
}
void JitArm64::ps_maddsX(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITPairedOff);
FALLBACK_IF(inst.Rc);
FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
bool upper = inst.SUBOP5 == 15;
ARM64Reg VA = fpr.R(a, REG_REG);
ARM64Reg VB = fpr.R(b, REG_REG);
ARM64Reg VC = fpr.R(c, REG_REG);
ARM64Reg VD = fpr.RW(d, REG_REG);
ARM64Reg V0 = fpr.GetReg();
m_float_emit.DUP(64, V0, VC, upper ? 1 : 0);
m_float_emit.FMUL(64, V0, V0, VA);
m_float_emit.FADD(64, VD, V0, VB);
fpr.FixSinglePrecision(d);
fpr.Unlock(V0);
}
void JitArm64::ps_msub(UGeckoInstruction inst) void JitArm64::ps_msub(UGeckoInstruction inst)
{ {
@ -243,7 +242,7 @@ void JitArm64::ps_sel(UGeckoInstruction inst)
} }
} }
void JitArm64::ps_sum0(UGeckoInstruction inst) void JitArm64::ps_sumX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff); JITDISABLE(bJITPairedOff);
@ -252,36 +251,7 @@ void JitArm64::ps_sum0(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
ARM64Reg VA = fpr.R(a, REG_REG); bool upper = inst.SUBOP5 == 11;
ARM64Reg VB = fpr.R(b, REG_REG);
ARM64Reg VC = fpr.R(c, REG_REG);
ARM64Reg VD = fpr.RW(d, REG_REG);
ARM64Reg V0 = fpr.GetReg();
m_float_emit.DUP(64, V0, VB, 1);
if (d != c)
{
m_float_emit.FADD(64, VD, V0, VA);
m_float_emit.INS(64, VD, 1, VC, 1);
}
else
{
m_float_emit.FADD(64, V0, V0, VA);
m_float_emit.INS(64, VD, 0, V0, 0);
}
fpr.FixSinglePrecision(d);
fpr.Unlock(V0);
}
void JitArm64::ps_sum1(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITPairedOff);
FALLBACK_IF(inst.Rc);
FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF);
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
ARM64Reg VA = fpr.R(a, REG_REG); ARM64Reg VA = fpr.R(a, REG_REG);
ARM64Reg VB = fpr.R(b, REG_REG); ARM64Reg VB = fpr.R(b, REG_REG);
@ -289,16 +259,16 @@ void JitArm64::ps_sum1(UGeckoInstruction inst)
ARM64Reg VD = fpr.RW(d, REG_REG); ARM64Reg VD = fpr.RW(d, REG_REG);
ARM64Reg V0 = fpr.GetReg(); ARM64Reg V0 = fpr.GetReg();
m_float_emit.DUP(64, V0, VA, 0); m_float_emit.DUP(64, V0, upper ? VA : VB, upper ? 0 : 1);
if (d != c) if (d != c)
{ {
m_float_emit.FADD(64, VD, V0, VB); m_float_emit.FADD(64, VD, V0, upper ? VB : VA);
m_float_emit.INS(64, VD, 0, VC, 0); m_float_emit.INS(64, VD, upper ? 0 : 1, VC, upper ? 0 : 1);
} }
else else
{ {
m_float_emit.FADD(64, V0, V0, VB); m_float_emit.FADD(64, V0, V0, upper ? VB : VA);
m_float_emit.INS(64, VD, 1, V0, 1); m_float_emit.INS(64, VD, upper ? 1 : 0, V0, upper ? 1 : 0);
} }
fpr.FixSinglePrecision(d); fpr.FixSinglePrecision(d);

4
Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
View File

@ -120,8 +120,8 @@ static GekkoOPTemplate table4[] =
static GekkoOPTemplate table4_2[] = static GekkoOPTemplate table4_2[] =
{ {
{10, &JitArm64::ps_sum0}, // ps_sum0 {10, &JitArm64::ps_sumX}, // ps_sum0
{11, &JitArm64::ps_sum1}, // ps_sum1 {11, &JitArm64::ps_sumX}, // ps_sum1
{12, &JitArm64::ps_mulsX}, // ps_muls0 {12, &JitArm64::ps_mulsX}, // ps_muls0
{13, &JitArm64::ps_mulsX}, // ps_muls1 {13, &JitArm64::ps_mulsX}, // ps_muls1
{14, &JitArm64::ps_maddsX}, // ps_madds0 {14, &JitArm64::ps_maddsX}, // ps_madds0