JitCache: Get rid of pointer casts
Silences more ubsan runtime asserts
This commit is contained in:
parent
955bef226e
commit
8aac59418b
|
@ -9,6 +9,7 @@
|
|||
// performance hit, it's not enabled by default, but it's useful for
|
||||
// locating performance issues.
|
||||
|
||||
#include <cstring>
|
||||
#include "disasm.h"
|
||||
|
||||
#include "Common/CommonTypes.h"
|
||||
|
@ -109,8 +110,8 @@ using namespace Gen;
|
|||
{
|
||||
blockCodePointers[block_num] = code_ptr;
|
||||
JitBlock &b = blocks[block_num];
|
||||
u32* icp = GetICachePtr(b.originalAddress);
|
||||
*icp = block_num;
|
||||
|
||||
std::memcpy(GetICachePtr(b.originalAddress), &block_num, sizeof(u32));
|
||||
|
||||
// Convert the logical address to a physical address for the block map
|
||||
u32 pAddr = b.originalAddress & 0x1FFFFFFF;
|
||||
|
@ -140,19 +141,22 @@ using namespace Gen;
|
|||
return blockCodePointers.data();
|
||||
}
|
||||
|
||||
u32* JitBaseBlockCache::GetICachePtr(u32 addr)
|
||||
u8* JitBaseBlockCache::GetICachePtr(u32 addr)
|
||||
{
|
||||
if (addr & JIT_ICACHE_VMEM_BIT)
|
||||
return (u32*)(&jit->GetBlockCache()->iCacheVMEM[addr & JIT_ICACHE_MASK]);
|
||||
else if (addr & JIT_ICACHE_EXRAM_BIT)
|
||||
return (u32*)(&jit->GetBlockCache()->iCacheEx[addr & JIT_ICACHEEX_MASK]);
|
||||
else
|
||||
return (u32*)(&jit->GetBlockCache()->iCache[addr & JIT_ICACHE_MASK]);
|
||||
return &jit->GetBlockCache()->iCacheVMEM[addr & JIT_ICACHE_MASK];
|
||||
|
||||
if (addr & JIT_ICACHE_EXRAM_BIT)
|
||||
return &jit->GetBlockCache()->iCacheEx[addr & JIT_ICACHEEX_MASK];
|
||||
|
||||
return &jit->GetBlockCache()->iCache[addr & JIT_ICACHE_MASK];
|
||||
}
|
||||
|
||||
int JitBaseBlockCache::GetBlockNumberFromStartAddress(u32 addr)
|
||||
{
|
||||
u32 inst = *GetICachePtr(addr);
|
||||
u32 inst;
|
||||
std::memcpy(&inst, GetICachePtr(addr), sizeof(u32));
|
||||
|
||||
if (inst & 0xfc000000) // definitely not a JIT block
|
||||
return -1;
|
||||
|
||||
|
@ -251,7 +255,7 @@ using namespace Gen;
|
|||
return;
|
||||
}
|
||||
b.invalid = true;
|
||||
*GetICachePtr(b.originalAddress) = JIT_ICACHE_INVALID_WORD;
|
||||
std::memcpy(GetICachePtr(b.originalAddress), &JIT_ICACHE_INVALID_WORD, sizeof(u32));
|
||||
|
||||
UnlinkBlock(block_num);
|
||||
|
||||
|
@ -284,7 +288,8 @@ using namespace Gen;
|
|||
while (it2 != block_map.end() && it2->first.second < pAddr + length)
|
||||
{
|
||||
JitBlock &b = blocks[it2->second];
|
||||
*GetICachePtr(b.originalAddress) = JIT_ICACHE_INVALID_WORD;
|
||||
std::memcpy(GetICachePtr(b.originalAddress), &JIT_ICACHE_INVALID_WORD, sizeof(u32));
|
||||
|
||||
DestroyBlock(it2->second, true);
|
||||
++it2;
|
||||
}
|
||||
|
|
|
@ -17,15 +17,16 @@
|
|||
// the only way to invalidate a region is the "icbi" instruction
|
||||
#define JIT_UNLIMITED_ICACHE
|
||||
|
||||
#define JIT_ICACHE_SIZE 0x2000000
|
||||
#define JIT_ICACHE_MASK 0x1ffffff
|
||||
#define JIT_ICACHEEX_SIZE 0x4000000
|
||||
#define JIT_ICACHEEX_MASK 0x3ffffff
|
||||
#define JIT_ICACHE_EXRAM_BIT 0x10000000
|
||||
#define JIT_ICACHE_VMEM_BIT 0x20000000
|
||||
// this corresponds to opcode 5 which is invalid in PowerPC
|
||||
#define JIT_ICACHE_INVALID_BYTE 0x80
|
||||
#define JIT_ICACHE_INVALID_WORD 0x80808080
|
||||
static const u32 JIT_ICACHE_SIZE = 0x2000000;
|
||||
static const u32 JIT_ICACHE_MASK = 0x1ffffff;
|
||||
static const u32 JIT_ICACHEEX_SIZE = 0x4000000;
|
||||
static const u32 JIT_ICACHEEX_MASK = 0x3ffffff;
|
||||
static const u32 JIT_ICACHE_EXRAM_BIT = 0x10000000;
|
||||
static const u32 JIT_ICACHE_VMEM_BIT = 0x20000000;
|
||||
|
||||
// This corresponds to opcode 5 which is invalid in PowerPC
|
||||
static const u32 JIT_ICACHE_INVALID_BYTE = 0x80;
|
||||
static const u32 JIT_ICACHE_INVALID_WORD = 0x80808080;
|
||||
|
||||
struct JitBlock
|
||||
{
|
||||
|
@ -116,7 +117,7 @@ class JitBaseBlockCache
|
|||
void LinkBlock(int i);
|
||||
void UnlinkBlock(int i);
|
||||
|
||||
u32* GetICachePtr(u32 addr);
|
||||
u8* GetICachePtr(u32 addr);
|
||||
void DestroyBlock(int block_num, bool invalidate);
|
||||
|
||||
// Virtual for overloaded
|
||||
|
|
Loading…
Reference in New Issue