Merge pull request #751 from FioraAeterna/fixsignext
JIT64: correctly sign-extend immediate RC values
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commit
88934fdef8
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@ -122,8 +122,7 @@ void Jit64::ComputeRC(const Gen::OpArg & arg)
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{
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if (arg.IsImm())
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{
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MOV(32, R(EAX), Imm32((s32)arg.offset));
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MOV(64, M(&PowerPC::ppcState.cr_val[0]), R(RAX));
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MOV(64, M(&PowerPC::ppcState.cr_val[0]), Imm32((s32)arg.offset));
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}
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else
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{
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@ -394,7 +393,7 @@ void Jit64::cmpXX(UGeckoInstruction inst)
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if (signedCompare)
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{
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if (gpr.R(a).IsImm())
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MOV(64, R(RAX), gpr.R(a));
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MOV(64, R(RAX), Imm32((s32)gpr.R(a).offset));
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else
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MOVSX(64, 32, RAX, gpr.R(a));
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if (!comparand.IsImm())
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@ -406,7 +405,7 @@ void Jit64::cmpXX(UGeckoInstruction inst)
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else
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{
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if (gpr.R(a).IsImm())
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MOV(32, R(RAX), gpr.R(a));
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MOV(32, R(RAX), Imm32((u32)gpr.R(a).offset));
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else
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MOVZX(64, 32, RAX, gpr.R(a));
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