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[ARM] Implement LFD. Reorder VFP register allocation a bit.

This commit is contained in:
Ryan Houdek 2013-07-17 04:23:38 -05:00
parent dc66b3d474
commit 86826b28dc
4 changed files with 45 additions and 13 deletions
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1
Source/Core/Core/Src/PowerPC/JitArm32/Jit.h
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@ -189,6 +189,7 @@ public:
// Floating point loadStore // Floating point loadStore
void lfs(UGeckoInstruction _inst); void lfs(UGeckoInstruction _inst);
void lfd(UGeckoInstruction _inst);
}; };
#endif // _JIT64_H #endif // _JIT64_H

47
Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
View File

@ -53,20 +53,51 @@ void JitArm::lfs(UGeckoInstruction inst)
else else
MOVI2R(rB, (u32)inst.SIMM_16); MOVI2R(rB, (u32)inst.SIMM_16);
MOVI2R(rA, (u32)&Memory::Read_U32); ARMReg v0 = fpr.R0(inst.FD, false);
ARMReg v1 = fpr.R1(inst.FD, false);
MOVI2R(rA, (u32)&Memory::Read_F32);
PUSH(4, R0, R1, R2, R3); PUSH(4, R0, R1, R2, R3);
MOV(R0, rB); MOV(R0, rB);
BL(rA); BL(rA);
MOV(rA, R0); // XXX: Need to use VCVT here.
VMOV(v0, D0);
VMOV(v1, D0);
POP(4, R0, R1, R2, R3); POP(4, R0, R1, R2, R3);
ARMReg v0 = fpr.R0(inst.FD, false);
ARMReg v1 = fpr.R1(inst.FD, false);
VMOV(v0, rA, false);
VMOV(v1, rA, false);
gpr.Unlock(rA, rB); gpr.Unlock(rA, rB);
SetJumpTarget(DoNotLoad); SetJumpTarget(DoNotLoad);
} }
void JitArm::lfd(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(LoadStoreFloating)
ARMReg rA = gpr.GetReg();
ARMReg rB = gpr.GetReg();
LDR(rA, R9, PPCSTATE_OFF(Exceptions));
CMP(rA, EXCEPTION_DSI);
FixupBranch DoNotLoad = B_CC(CC_EQ);
if (inst.RA)
{
MOVI2R(rB, inst.SIMM_16);
ARMReg RA = gpr.R(inst.RA);
ADD(rB, rB, RA);
}
else
MOVI2R(rB, (u32)inst.SIMM_16);
ARMReg v0 = fpr.R0(inst.FD, false);
MOVI2R(rA, (u32)&Memory::Read_F64);
PUSH(4, R0, R1, R2, R3);
MOV(R0, rB);
BL(rA);
VMOV(v0, D0);
POP(4, R0, R1, R2, R3);
gpr.Unlock(rA, rB);
SetJumpTarget(DoNotLoad);
}

2
Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp
View File

@ -99,7 +99,7 @@ static GekkoOPTemplate primarytable[] =
{48, &JitArm::lfs}, //"lfs", OPTYPE_LOADFP, FL_IN_A}}, {48, &JitArm::lfs}, //"lfs", OPTYPE_LOADFP, FL_IN_A}},
{49, &JitArm::Default}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, {49, &JitArm::Default}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},
{50, &JitArm::Default}, //"lfd", OPTYPE_LOADFP, FL_IN_A}}, {50, &JitArm::lfd}, //"lfd", OPTYPE_LOADFP, FL_IN_A}},
{51, &JitArm::Default}, //"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, {51, &JitArm::Default}, //"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},
{52, &JitArm::Default}, //"stfs", OPTYPE_STOREFP, FL_IN_A}}, {52, &JitArm::Default}, //"stfs", OPTYPE_STOREFP, FL_IN_A}},

8
Source/Core/Core/Src/PowerPC/JitArm32/JitFPRCache.cpp
View File

@ -56,9 +56,9 @@ ARMReg *ArmFPRCache::GetPPCAllocationOrder(int &count)
// the ppc side. // the ppc side.
static ARMReg allocationOrder[] = static ARMReg allocationOrder[] =
{ {
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13,
D11, D12, D13, D14, D15, D16, D17, D18, D19, D14, D15, D16, D17, D18, D19, D20, D21, D22,
D20, D21, D22, D23, D24, D25, D26, D27 D23, D24, D25, D26, D27, D28, D29, D30, D31
}; };
count = sizeof(allocationOrder) / sizeof(const int); count = sizeof(allocationOrder) / sizeof(const int);
return allocationOrder; return allocationOrder;
@ -69,7 +69,7 @@ ARMReg *ArmFPRCache::GetAllocationOrder(int &count)
// the host side. // the host side.
static ARMReg allocationOrder[] = static ARMReg allocationOrder[] =
{ {
D31, D30, D29, D28 D0, D1, D2, D3
}; };
count = sizeof(allocationOrder) / sizeof(const int); count = sizeof(allocationOrder) / sizeof(const int);
return allocationOrder; return allocationOrder;