Merge pull request #6641 from BhaaLseN/dsp-update
docs: Update the GameCube DSP User's Manual
This commit is contained in:
Mat M
GitHub
commit
865d737efd
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@ -46,7 +46,7 @@
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% Document front page material
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\title{\textbf{\Huge GameCube DSP User's Manual}}
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\author{Reverse-engineered and documented by Duddie \\ \href{mailto:duddie@walla.com}{duddie@walla.com}}
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\date{\today\\v0.0.5}
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\date{\today\\v0.0.6}
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% Title formatting commands
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\newcommand{\OpcodeTitle}[1]{\subsection{\textbf{\Large #1}}}
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@ -238,6 +238,7 @@ The purpose of this documentation is purely academic and it aims at understandin
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0.0.3 & 2005.05.09 & Duddie & Fixed BLOOP and BLOOPI and added description of the loop stack. \\ \hline
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0.0.4 & 2005.05.12 & Duddie & Added preliminary DSP memory map and opcode syntax. \\ \hline
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0.0.5 & 2018.04.09 & Lioncache & Converted document over to LaTeX. \\ \hline
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0.0.6 & 2018.04.13 & BhaaL & Updated register tables, fixed opcode operations \\ \hline
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\end{tabular}
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\end{table}
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@ -400,39 +401,39 @@ The DSP has 32 16-bit registers, although their individual purpose and their fun
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\centering
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\begin{tabular}{|l|l|l|l|}
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\hline
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& & & \\ \hline
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\Register{\$0} & \Register{\$r00} & \Register{\$ar0} & Addressing register 0 \\ \hline
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\Register{\$1} & \Register{\$r01} & \Register{\$ar1} & \\ \hline
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\Register{\$2} & \Register{\$r02} & \Register{\$ar2} & \\ \hline
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\Register{\$3} & \Register{\$r03} & \Register{\$ar3} & \\ \hline
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\Register{\$4} & \Register{\$r04} & \Register{\$ix0} & \\ \hline
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\Register{\$5} & \Register{\$r05} & \Register{\$ix1} & \\ \hline
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\Register{\$6} & \Register{\$r06} & \Register{\$ix2} & \\ \hline
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\Register{\$7} & \Register{\$r07} & \Register{\$ix3} & \\ \hline
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\Register{\$8} & \Register{\$r08} & & \\ \hline
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\Register{\$9} & \Register{\$r09} & & \\ \hline
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\Register{\$10} & \Register{\$r0A} & & \\ \hline
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\Register{\$11} & \Register{\$r0B} & & \\ \hline
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\Register{\$12} & \Register{\$r0C} & \Register{\$st0} & \\ \hline
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\Register{\$13} & \Register{\$r0D} & \Register{\$st1} & \\ \hline
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\Register{\$14} & \Register{\$r0E} & \Register{\$st2} & \\ \hline
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\Register{\$15} & \Register{\$r0F} & \Register{\$st3} & \\ \hline
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\Register{\$16} & \Register{\$r10} & \Register{\$ac0.h} & \\ \hline
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\Register{\$17} & \Register{\$r11} & \Register{\$ac1.h} & \\ \hline
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\Register{\$18} & \Register{\$r12} & \Register{\$config} & \\ \hline
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\Register{\$19} & \Register{\$r13} & \Register{\$sr} & \\ \hline
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\Register{\$20} & \Register{\$r14} & \Register{\$prod.l} & \\ \hline
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\Register{\$21} & \Register{\$r15} & \Register{\$prod.m1} & \\ \hline
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\Register{\$22} & \Register{\$r16} & \Register{\$prod.h} & \\ \hline
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\Register{\$23} & \Register{\$r17} & \Register{\$prod.m2} & \\ \hline
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\Register{\$24} & \Register{\$r18} & \Register{\$ax0.l} & \\ \hline
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\Register{\$25} & \Register{\$r19} & \Register{\$ax0.h} & \\ \hline
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\Register{\$26} & \Register{\$r1A} & \Register{\$ax1.l} & \\ \hline
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\Register{\$27} & \Register{\$r1B} & \Register{\$ax1.h} & \\ \hline
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\Register{\$28} & \Register{\$r1C} & \Register{\$ac0.l} & \\ \hline
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\Register{\$29} & \Register{\$r1D} & \Register{\$ac1.l} & \\ \hline
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\Register{\$30} & \Register{\$r1E} & \Register{\$ac0.m} & \\ \hline
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\Register{\$31} & \Register{\$r1F} & \Register{\$ac1.m} & \\ \hline
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& & & \\ \hline
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\Register{\$0} & \Register{\$r00} & \Register{\$ar0} & Addressing register 0 \\ \hline
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\Register{\$1} & \Register{\$r01} & \Register{\$ar1} & Addressing register 1 \\ \hline
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\Register{\$2} & \Register{\$r02} & \Register{\$ar2} & Addressing register 2 \\ \hline
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\Register{\$3} & \Register{\$r03} & \Register{\$ar3} & Addressing register 3 \\ \hline
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\Register{\$4} & \Register{\$r04} & \Register{\$ix0} & Indexing register 0 \\ \hline
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\Register{\$5} & \Register{\$r05} & \Register{\$ix1} & Indexing register 1 \\ \hline
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\Register{\$6} & \Register{\$r06} & \Register{\$ix2} & Indexing register 2 \\ \hline
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\Register{\$7} & \Register{\$r07} & \Register{\$ix3} & Indexing register 3 \\ \hline
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\Register{\$8} & \Register{\$r08} & & \\ \hline
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\Register{\$9} & \Register{\$r09} & & \\ \hline
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\Register{\$10} & \Register{\$r0A} & & \\ \hline
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\Register{\$11} & \Register{\$r0B} & & \\ \hline
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\Register{\$12} & \Register{\$r0C} & \Register{\$st0} & Call stack register \\ \hline
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\Register{\$13} & \Register{\$r0D} & \Register{\$st1} & Data stack register \\ \hline
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\Register{\$14} & \Register{\$r0E} & \Register{\$st2} & Loop address stack register \\ \hline
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\Register{\$15} & \Register{\$r0F} & \Register{\$st3} & Loop counter register \\ \hline
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\Register{\$16} & \Register{\$r10} & \Register{\$ac0.h} & 40-bit Accumulator 0 (high) \\ \hline
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\Register{\$17} & \Register{\$r11} & \Register{\$ac1.h} & 40-bit Accumulator 1 (high) \\ \hline
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\Register{\$18} & \Register{\$r12} & \Register{\$config} & Config register \\ \hline
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\Register{\$19} & \Register{\$r13} & \Register{\$sr} & Status register \\ \hline
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\Register{\$20} & \Register{\$r14} & \Register{\$prod.l} & Product register (low) \\ \hline
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\Register{\$21} & \Register{\$r15} & \Register{\$prod.m1} & Product register (mid 1) \\ \hline
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\Register{\$22} & \Register{\$r16} & \Register{\$prod.h} & Product register (high) \\ \hline
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\Register{\$23} & \Register{\$r17} & \Register{\$prod.m2} & Product register (mid 2) \\ \hline
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\Register{\$24} & \Register{\$r18} & \Register{\$ax0.l} & 32-bit Accumulator 0 (low) \\ \hline
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\Register{\$25} & \Register{\$r19} & \Register{\$ax0.h} & 32-bit Accumulator 0 (high) \\ \hline
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\Register{\$26} & \Register{\$r1A} & \Register{\$ax1.l} & 32-bit Accumulator 1 (low) \\ \hline
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\Register{\$27} & \Register{\$r1B} & \Register{\$ax1.h} & 32-bit Accumulator 1 (high) \\ \hline
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\Register{\$28} & \Register{\$r1C} & \Register{\$ac0.l} & 40-bit Accumulator 0 (low) \\ \hline
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\Register{\$29} & \Register{\$r1D} & \Register{\$ac1.l} & 40-bit Accumulator 1 (low) \\ \hline
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\Register{\$30} & \Register{\$r1E} & \Register{\$ac0.m} & 40-bit Accumulator 0 (mid) \\ \hline
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\Register{\$31} & \Register{\$r1F} & \Register{\$ac1.m} & 40-bit Accumulator 1 (mid) \\ \hline
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\end{tabular}
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\end{table}
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@ -502,14 +503,23 @@ Furthermore, it also contains control bits to configure the flow of certain oper
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\centering
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\begin{tabular}{|l|l|l|}
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\hline
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\textbf{Bit} & \textbf{Name} & \textbf{Comment} \\ \hline
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\texttt{14} & \texttt{AM} & Product multiply result by 2 (when \texttt{AM = 0}) \\ \hline
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\texttt{9} & \texttt{IE} & Interrupt enable \\ \hline
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\texttt{8} & \texttt{0} & Hardwired to 0? \\ \hline
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\texttt{6} & \texttt{LZ} & Logic zero \\ \hline
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\texttt{4} & \texttt{AS} & \\ \hline
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\texttt{3} & \texttt{S} & Sign \\ \hline
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\texttt{2} & \texttt{Z} & Zero \\ \hline
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\textbf{Bit} & \textbf{Name} & \textbf{Comment} \\ \hline
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\texttt{15} & \texttt{SU} & Operands are signed (1 = unsigned) \\ \hline
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\texttt{14} & \texttt{SXM} & Sign extension mode (0 = \texttt{set16}, 1 = \texttt{set40}) \\ \hline
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\texttt{13} & \texttt{AM} & Product multiply result by 2 (when \texttt{AM = 0}) \\ \hline
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\texttt{12} & & \\ \hline
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\texttt{11} & \texttt{EIE} & External interrupt enable \\ \hline
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\texttt{10} & & \\ \hline
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\texttt{9} & \texttt{IE} & Interrupt enable \\ \hline
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\texttt{8} & \texttt{0} & Hardwired to 0? \\ \hline
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\texttt{7} & \texttt{OS} & Overflow (sticky) \\ \hline
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\texttt{6} & \texttt{LZ} & Logic zero \\ \hline
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\texttt{5} & & Top two bits are equal \\ \hline
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\texttt{4} & \texttt{AS} & Above s32 \\ \hline
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\texttt{3} & \texttt{S} & Sign \\ \hline
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\texttt{2} & \texttt{Z} & Arithmetic zero \\ \hline
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\texttt{1} & \texttt{O} & Overflow \\ \hline
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\texttt{0} & \texttt{C} & Carry \\ \hline
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\end{tabular}
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\end{table}
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@ -558,15 +568,15 @@ Exception vectors are located at address \Address{0x0000} in Instruction RAM.
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\centering
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\begin{tabular}{|l|l|l|l|}
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\hline
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\textbf{Level} & \textbf{Address} & \textbf{Name} & \textbf{Description} \\ \hline
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0 & \Address{0x0000} & \texttt{RESET} & \\ \hline
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1 & \Address{0x0002} & \texttt{STOVF} & Stack under/overflow \\ \hline
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2 & \Address{0x0004} & & \\ \hline
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3 & \Address{0x0006} & & \\ \hline
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4 & \Address{0x0008} & & \\ \hline
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5 & \Address{0x000A} & \texttt{ACCOV} & Accelerator address overflow \\ \hline
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6 & \Address{0x000C} & & \\ \hline
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7 & \Address{0x000E} & & \\ \hline
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\textbf{Level} & \textbf{Address} & \textbf{Name} & \textbf{Description} \\ \hline
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0 & \Address{0x0000} & \texttt{RESET} & \\ \hline
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1 & \Address{0x0002} & \texttt{STOVF} & Stack under/overflow \\ \hline
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2 & \Address{0x0004} & & \\ \hline
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3 & \Address{0x0006} & & \\ \hline
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4 & \Address{0x0008} & & \\ \hline
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5 & \Address{0x000A} & \texttt{ACCOV} & Accelerator address overflow \\ \hline
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6 & \Address{0x000C} & & \\ \hline
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7 & \Address{0x000E} & \texttt{INT} & External interrupt (from CPU) \\ \hline
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\end{tabular}
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\end{table}
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@ -855,21 +865,21 @@ The groups of conditional instructions are, \Opcode{CALL}, \Opcode{JMP}, \Opcode
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\begin{tabular}{|l|l|l|l|}
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\hline
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\textbf{Bits} & \textbf{\texttt{cc}} & \textbf{Name} & \textbf{Evaluated expression} \\ \hline
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\texttt{0b0000} & & & \\ \hline
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\texttt{0b0001} & & & \\ \hline
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\texttt{0b0010} & & & \\ \hline
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\texttt{0b0011} & & & \\ \hline
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\texttt{0b0100} & \texttt{EQ} & Equal & \\ \hline
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\texttt{0b0101} & \texttt{NE} & Not equal & \\ \hline
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\texttt{0b0110} & & & \\ \hline
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\texttt{0b0111} & & & \\ \hline
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\texttt{0b1000} & & & \\ \hline
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\texttt{0b1001} & & & \\ \hline
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\texttt{0b0000} & \texttt{GE} & Greater than or equal & \\ \hline
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\texttt{0b0001} & \texttt{L} & Less than & \\ \hline
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\texttt{0b0010} & \texttt{G} & Greater than & \\ \hline
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\texttt{0b0011} & \texttt{LE} & Less than or equal & \\ \hline
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\texttt{0b0100} & \texttt{NE} & Not equal & \texttt{(\$sr \& 0x4) == 0} \\ \hline
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\texttt{0b0101} & \texttt{EQ} & Equal & \texttt{(\$sr \& 0x4) != 0} \\ \hline
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\texttt{0b0110} & \texttt{NC} & Not carry & \texttt{(\$sr \& 0x1) == 0} \\ \hline
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\texttt{0b0111} & \texttt{C} & Carry & \texttt{(\$sr \& 0x1) != 0} \\ \hline
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\texttt{0b1000} & & Below s32 & \texttt{(\$sr \& 0x10) == 0} \\ \hline
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\texttt{0b1001} & & Above s32 & \texttt{(\$sr \& 0x10) != 0} \\ \hline
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\texttt{0b1010} & & & \\ \hline
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\texttt{0b1011} & & & \\ \hline
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\texttt{0b1100} & \texttt{ZR} & Zero & \texttt{(\$sr \& 0x40) != 0} \\ \hline
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\texttt{0b1101} & \texttt{NZ} & Not zero & \texttt{(\$sr \& 0x40) == 0} \\ \hline
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\texttt{0b1110} & & & \\ \hline
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\texttt{0b1100} & \texttt{NZ} & Not zero & \texttt{(\$sr \& 0x40) == 0} \\ \hline
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\texttt{0b1101} & \texttt{ZR} & Zero & \texttt{(\$sr \& 0x40) != 0} \\ \hline
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\texttt{0b1110} & \texttt{O} & Overflow & \texttt{(\$sr \& 0x2) != 0} \\ \hline
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\texttt{0b1111} & & \textless always\textgreater & \\ \hline
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\end{tabular}
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\end{table}
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@ -981,7 +991,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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\begin{DSPOpcodeOperation}
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$acD.hm += #I
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FLAGS($acD)
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$pc++
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$pc += 2
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\end{DSPOpcodeOperation}
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\end{DSPOpcode}
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@ -1109,7 +1119,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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ELSE
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$sr.LZ = 0
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ENDIF
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$pc++
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$pc += 2
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\end{DSPOpcodeOperation}
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\end{DSPOpcode}
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@ -1135,7 +1145,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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ELSE
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$sr.LZ = 0
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ENDIF
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$pc++
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$pc += 2
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\end{DSPOpcodeOperation}
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\end{DSPOpcode}
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@ -1156,7 +1166,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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\begin{DSPOpcodeOperation}
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$acD.m &= #I
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FLAGS($acD)
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$pc++
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$pc += 2
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\end{DSPOpcodeOperation}
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\end{DSPOpcode}
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@ -1261,7 +1271,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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$st0 = $pc + 2
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$st2 = addrA
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$st3 = $R
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$pc + 2
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$pc += 2
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// On real hardware, the below does not happen,
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// this opcode only sets stack registers
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@ -1297,7 +1307,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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$st0 = $pc + 2
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$st2 = addrA
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$st3 = I
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$pc + 2
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$pc += 2
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// On real hardware, the below does not happen,
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// this opcode only sets stack registers
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@ -1490,7 +1500,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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\begin{DSPOpcodeOperation}
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res = ($acD.hm - I) | $acD.l
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FLAGS(res)
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$pc++
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$pc += 2
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\end{DSPOpcodeOperation}
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\end{DSPOpcode}
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@ -2030,7 +2040,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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\begin{DSPOpcodeOperation}
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$(0x18+D) = MEM[M]
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$pc += 2
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$pc++
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\end{DSPOpcodeOperation}
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\end{DSPOpcode}
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@ -2812,7 +2822,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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\begin{DSPOpcodeOperation}
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$acD.m |= #I
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FLAGS($acD)
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$pc++
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$pc += 2
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\end{DSPOpcodeOperation}
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\end{DSPOpcode}
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@ -3079,7 +3089,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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\begin{DSPOpcodeOperation}
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MEM[M] = $(0x18+S)
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$pc += 2
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$pc++
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\end{DSPOpcodeOperation}
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\end{DSPOpcode}
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@ -3218,7 +3228,7 @@ There are two pairs of conditions that work similar: \texttt{EQ}/\texttt{NE} and
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\begin{DSPOpcodeOperation}
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$acD.m ^= #I
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FLAGS($acD)
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$pc++
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$pc += 2
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\end{DSPOpcodeOperation}
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\end{DSPOpcode}
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@ -3375,13 +3385,13 @@ allow extending (8 lower bits of opcode not used by opcode). Extended opcodes do
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\end{DSPOpcodeOperation}
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\end{DSPOpcode}
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\begin{DSPOpcode}{'LSMN}
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\begin{DSPOpcode}{'LSNM}
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\begin{DSPOpcodeBytefield}{16}
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\monobitbox{4}{xxxx} & \monobitbox{4}{xxxx} & \monobitbox{4}{10dd} & \monobitbox{4}{110s}
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\end{DSPOpcodeBytefield}
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\begin{DSPOpcodeFormat}
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'LSMN $(0x18+D), $acS.m
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'LSNM $(0x18+D), $acS.m
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\end{DSPOpcodeFormat}
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\begin{DSPOpcodeDescription}
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@ -3494,8 +3504,8 @@ allow extending (8 lower bits of opcode not used by opcode). Extended opcodes do
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\end{DSPOpcodeDescription}
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\begin{DSPOpcodeOperation}
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$(0x18+D) = MEM[$ar0]
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MEM[$ar3] = $acS.m
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$(0x18+D) = MEM[$ar3]
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MEM[$ar0] = $acS.m
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$ar0++
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$ar3++
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\end{DSPOpcodeOperation}
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@ -3517,8 +3527,8 @@ allow extending (8 lower bits of opcode not used by opcode). Extended opcodes do
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\end{DSPOpcodeDescription}
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\begin{DSPOpcodeOperation}
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$(0x18+D) = MEM[$ar0]
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MEM[$ar3] = $acS.m
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$(0x18+D) = MEM[$ar3]
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MEM[$ar0] = $acS.m
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$ar0++
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$ar3 += $ix3
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\end{DSPOpcodeOperation}
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@ -3541,8 +3551,8 @@ allow extending (8 lower bits of opcode not used by opcode). Extended opcodes do
|
|||
\end{DSPOpcodeDescription}
|
||||
|
||||
\begin{DSPOpcodeOperation}
|
||||
$(0x18+D) = MEM[$ar0]
|
||||
MEM[$ar3] = $acS.m
|
||||
$(0x18+D) = MEM[$ar3]
|
||||
MEM[$ar0] = $acS.m
|
||||
$ar0 += $ix0
|
||||
$ar3 += $ix3
|
||||
\end{DSPOpcodeOperation}
|
||||
|
|
@ -3564,8 +3574,8 @@ allow extending (8 lower bits of opcode not used by opcode). Extended opcodes do
|
|||
\end{DSPOpcodeDescription}
|
||||
|
||||
\begin{DSPOpcodeOperation}
|
||||
$(0x18+D) = MEM[$ar0]
|
||||
MEM[$ar3] = $acS.m
|
||||
$(0x18+D) = MEM[$ar3]
|
||||
MEM[$ar0] = $acS.m
|
||||
$ar0 += $ix0
|
||||
$ar3++
|
||||
\end{DSPOpcodeOperation}
|
||||
|
|
|
|||
Loading…
Reference in New Issue