Make OpArg.offset and operandReg private.

Also cleaned up WriteRest function.

Source/Core/Common/x64Emitter.cpp

@@ -223,7 +223,7 @@ void OpArg::WriteRest(XEmitter *emit, int extraBytes, X64Reg _operandReg,
 		// Oh, no memory, Just a reg.
 		mod = 3; //11
 	}
-	else if (scale >= 1)
+	else
 	{
 		//Ah good, no scaling.
 		if (scale == SCALE_ATREG && !((_offsetOrBaseReg & 7) == 4 || (_offsetOrBaseReg & 7) == 5))
@@ -249,7 +249,7 @@ void OpArg::WriteRest(XEmitter *emit, int extraBytes, X64Reg _operandReg,
 			mod = 0;
 			_offsetOrBaseReg = 5;
 		}
-		else //if (scale != SCALE_ATREG)
+		else
 		{
 			if ((_offsetOrBaseReg & 7) == 4) //this would occupy the SIB encoding :(
 			{
@@ -288,10 +288,6 @@ void OpArg::WriteRest(XEmitter *emit, int extraBytes, X64Reg _operandReg,
 	if (SIB)
 		oreg = 4;
 
-	// TODO(ector): WTF is this if about? I don't remember writing it :-)
-	//if (RIP)
-	//    oreg = 5;
-
 	emit->WriteModRM(mod, _operandReg&7, oreg&7);
 
 	if (SIB)

Source/Core/Common/x64Emitter.h

@@ -128,6 +128,8 @@ class XEmitter;
 // RIP addressing does not benefit from micro op fusion on Core arch
 struct OpArg
 {
+	friend class XEmitter; // For accessing offset and operandReg
+
 	OpArg() {}  // dummy op arg, used for storage
 	OpArg(u64 _offset, int _scale, X64Reg rmReg = RAX, X64Reg scaledReg = RAX)
 	{
@@ -148,9 +150,6 @@ struct OpArg
 	void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=INVALID_REG, bool warn_64bit_offset = true) const;
 	void WriteFloatModRM(XEmitter *emit, FloatOp op);
 	void WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg operandReg, int bits);
-	// This one is public - must be written to
-	u64 offset;  // use RIP-relative as much as possible - Also used to store immediates.
-	u16 operandReg;
 
 	u64 Imm64() const { _dbg_assert_(DYNA_REC, scale == SCALE_IMM64); return (u64)offset; }
 	u32 Imm32() const { _dbg_assert_(DYNA_REC, scale == SCALE_IMM32); return (u32)offset; }
@@ -198,10 +197,20 @@ struct OpArg
 		else
 			return INVALID_REG;
 	}
+
+	void AddMemOffset(int val)
+	{
+		_dbg_assert_msg_(DYNA_REC, scale == SCALE_RIP || (scale <= SCALE_ATREG && scale > SCALE_NONE),
+		                 "Tried to increment an OpArg which doesn't have an offset");
+		offset += val;
+	}
+
 private:
 	u8 scale;
 	u16 offsetOrBaseReg;
 	u16 indexReg;
+	u64 offset;  // Also used to store immediates.
+	u16 operandReg;
 };
 
 template <typename T>

Source/Core/Core/PowerPC/Jit64/JitRegCache.cpp

@@ -354,10 +354,6 @@ void GPRRegCache::StoreRegister(size_t preg, OpArg newLoc)
 
 void FPURegCache::LoadRegister(size_t preg, X64Reg newLoc)
 {
-	if (!regs[preg].location.IsImm() && (regs[preg].location.offset & 0xF))
-	{
-		PanicAlert("WARNING - misaligned fp register location %u", (unsigned int) preg);
-	}
 	emit->MOVAPD(newLoc, regs[preg].location);
 }
 

Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp

@@ -178,7 +178,7 @@ OpArg Jit64::ExtractFromReg(int reg, int offset)
 	{
 		gpr.StoreFromRegister(reg, FLUSH_MAINTAIN_STATE);
 		src = gpr.GetDefaultLocation(reg);
-		src.offset += offset;
+		src.AddMemOffset(offset);
 	}
 	return src;
 }

Source/Core/Core/PowerPC/Jit64/Jit_LoadStorePaired.cpp

@@ -301,7 +301,7 @@ void Jit64::psq_lXX(UGeckoInstruction inst)
 
 	// Get the high part of the GQR register
 	OpArg gqr = PPCSTATE(spr[SPR_GQR0 + i]);
-	gqr.offset += 2;
+	gqr.AddMemOffset(2);
 
 	AND(32, R(RSCRATCH2), gqr);
 	MOVZX(32, 8, RSCRATCH, R(RSCRATCH2));

Source/Core/VideoCommon/VertexLoaderX64.cpp

@@ -244,7 +244,7 @@ void VertexLoaderX64::ReadColor(OpArg data, u64 attribute, int format)
 		case FORMAT_24B_6666:
 			//          RRRRRRGG GGGGBBBB BBAAAAAA
 			// AAAAAAAA BBBBBBBB GGGGGGGG RRRRRRRR
-			data.offset -= 1;
+			data.AddMemOffset(-1); // subtract one from address so we can use a 32bit load and bswap
 			LoadAndSwap(32, scratch1, data);
 			if (cpu_info.bBMI2)
 			{
@@ -346,10 +346,10 @@ void VertexLoaderX64::GenerateVertexLoader()
 			{
 				data = GetVertexAddr(ARRAY_NORMAL, m_VtxDesc.Normal);
 				int elem_size = 1 << (m_VtxAttr.NormalFormat / 2);
-				data.offset += i * elem_size * 3;
+				data.AddMemOffset(i * elem_size * 3);
 			}
-			data.offset += ReadVertex(data, m_VtxDesc.Normal, m_VtxAttr.NormalFormat, 3, 3,
+			data.AddMemOffset(ReadVertex(data, m_VtxDesc.Normal, m_VtxAttr.NormalFormat, 3, 3,
-			                          true, scaling_exponent, &m_native_vtx_decl.normals[i]);
+			                             true, scaling_exponent, &m_native_vtx_decl.normals[i]));
 		}
 
 		m_native_components |= VB_HAS_NRM0;