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Merge pull request #1060 from rohit-n/move-using 

JitArm32: Minor cleanup.
This commit is contained in:
Pierre Bourdon 2014-09-14 01:59:39 +02:00
parent eee473ed5f 428ee10463
commit 84a564a304
16 changed files with 74 additions and 57 deletions
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3
Source/Core/Core/PowerPC/JitArm32/Jit.cpp
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@ -5,7 +5,7 @@
#include <map>
#include "Common/ArmEmitter.h"
#include "Common/Common.h"
#include "Common/CommonTypes.h"
#include "Core/ConfigManager.h"
#include "Core/Core.h"
@ -23,7 +23,6 @@
#include "Core/PowerPC/JitArm32/JitArm_Tables.h"
using namespace ArmGen;
using namespace PowerPC;
static int CODE_SIZE = 1024*1024*32;

20
Source/Core/Core/PowerPC/JitArm32/Jit.h
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@ -53,11 +53,11 @@ private:
void PrintDebug(UGeckoInstruction inst, u32 level);
void Helper_UpdateCR1(ARMReg fpscr, ARMReg temp);
void Helper_UpdateCR1(ArmGen::ARMReg fpscr, ArmGen::ARMReg temp);
void SetFPException(ARMReg Reg, u32 Exception);
void SetFPException(ArmGen::ARMReg Reg, u32 Exception);
FixupBranch JumpIfCRFieldBit(int field, int bit, bool jump_if_set);
ArmGen::FixupBranch JumpIfCRFieldBit(int field, int bit, bool jump_if_set);
public:
JitArm() : code_buffer(32000) {}
~JitArm() {}
@ -102,25 +102,25 @@ public:
// Utilities for use by opcodes
void WriteExit(u32 destination);
void WriteExitDestInR(ARMReg Reg);
void WriteRfiExitDestInR(ARMReg Reg);
void WriteExitDestInR(ArmGen::ARMReg Reg);
void WriteRfiExitDestInR(ArmGen::ARMReg Reg);
void WriteExceptionExit();
void WriteCallInterpreter(UGeckoInstruction _inst);
void Cleanup();
void ComputeRC(ARMReg value, int cr = 0);
void ComputeRC(ArmGen::ARMReg value, int cr = 0);
void ComputeRC(s32 value, int cr);
void ComputeCarry();
void ComputeCarry(bool Carry);
void GetCarryAndClear(ARMReg reg);
void FinalizeCarry(ARMReg reg);
void GetCarryAndClear(ArmGen::ARMReg reg);
void FinalizeCarry(ArmGen::ARMReg reg);
// TODO: This shouldn't be here
void UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset);
void UnsafeStoreFromReg(ArmGen::ARMReg dest, ArmGen::ARMReg value, int accessSize, s32 offset);
void SafeStoreFromReg(bool fastmem, s32 dest, u32 value, s32 offsetReg, int accessSize, s32 offset);
void UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offsetReg, s32 offset);
void UnsafeLoadToReg(ArmGen::ARMReg dest, ArmGen::ARMReg addr, int accessSize, s32 offsetReg, s32 offset);
void SafeLoadToReg(bool fastmem, u32 dest, s32 addr, s32 offsetReg, int accessSize, s32 offset, bool signExtend, bool reverse);

4
Source/Core/Core/PowerPC/JitArm32/JitArm_BackPatch.cpp
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@ -4,13 +4,15 @@
#include <string>
#include "Common/Common.h"
#include "Common/CommonTypes.h"
#include "Common/StringUtil.h"
#include "Core/HW/Memmap.h"
#include "Core/PowerPC/JitArm32/Jit.h"
#include "Core/PowerPC/JitCommon/JitBackpatch.h"
using namespace ArmGen;
// This generates some fairly heavy trampolines, but:
// 1) It's really necessary. We don't know anything about the context.
// 2) It doesn't really hurt. Only instructions that access I/O will get these, and there won't be

2
Source/Core/Core/PowerPC/JitArm32/JitArm_Branch.cpp
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@ -3,7 +3,7 @@
// Refer to the license.txt file included.
#include "Common/ArmEmitter.h"
#include "Common/Common.h"
#include "Common/CommonTypes.h"
#include "Core/Core.h"
#include "Core/CoreTiming.h"

28
Source/Core/Core/PowerPC/JitArm32/JitArm_FPUtils.h
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@ -15,22 +15,22 @@ static const double minmaxFloat[2] = {-(double)0x80000000, (double)0x7FFFFFFF};
static const double doublenum = 0xfff8000000000000ull;
// Exception masks
static Operand2 FRFIMask(5, 0x8); // 0x60000
static Operand2 FIMask(2, 8); // 0x20000
static Operand2 FRMask(4, 8); // 0x40000
static Operand2 FXMask(2, 1); // 0x80000000
static Operand2 VEMask(0x40, 0); // 0x40
static ArmGen::Operand2 FRFIMask(5, 0x8); // 0x60000
static ArmGen::Operand2 FIMask(2, 8); // 0x20000
static ArmGen::Operand2 FRMask(4, 8); // 0x40000
static ArmGen::Operand2 FXMask(2, 1); // 0x80000000
static ArmGen::Operand2 VEMask(0x40, 0); // 0x40
static Operand2 XXException(2, 4); // 0x2000000
static Operand2 CVIException(1, 0xC); // 0x100
static Operand2 NANException(1, 4); // 0x1000000
static Operand2 VXVCException(8, 8); // 0x80000
static Operand2 ZXException(1, 3); // 0x4000000
static Operand2 VXSQRTException(2, 5); // 0x200
static ArmGen::Operand2 XXException(2, 4); // 0x2000000
static ArmGen::Operand2 CVIException(1, 0xC); // 0x100
static ArmGen::Operand2 NANException(1, 4); // 0x1000000
static ArmGen::Operand2 VXVCException(8, 8); // 0x80000
static ArmGen::Operand2 ZXException(1, 3); // 0x4000000
static ArmGen::Operand2 VXSQRTException(2, 5); // 0x200
inline void JitArm::SetFPException(ARMReg Reg, u32 Exception)
inline void JitArm::SetFPException(ArmGen::ARMReg Reg, u32 Exception)
{
Operand2 *ExceptionMask;
ArmGen::Operand2 *ExceptionMask;
switch (Exception)
{
case FPSCR_VXCVI:
@ -56,7 +56,7 @@ inline void JitArm::SetFPException(ARMReg Reg, u32 Exception)
return;
break;
}
ARMReg rB = gpr.GetReg();
ArmGen::ARMReg rB = gpr.GetReg();
MOV(rB, Reg);
ORR(Reg, Reg, *ExceptionMask);
CMP(rB, Reg);

4
Source/Core/Core/PowerPC/JitArm32/JitArm_FloatingPoint.cpp
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@ -3,7 +3,7 @@
// Refer to the license.txt file included.
#include "Common/ArmEmitter.h"
#include "Common/Common.h"
#include "Common/CommonTypes.h"
#include "Core/ConfigManager.h"
#include "Core/Core.h"
@ -17,6 +17,8 @@
#include "Core/PowerPC/JitArm32/JitFPRCache.h"
#include "Core/PowerPC/JitArm32/JitRegCache.h"
using namespace ArmGen;
void JitArm::Helper_UpdateCR1(ARMReg fpscr, ARMReg temp)
{
}

4
Source/Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp
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@ -3,7 +3,7 @@
// Refer to the license.txt file included.
#include "Common/ArmEmitter.h"
#include "Common/Common.h"
#include "Common/CommonTypes.h"
#include "Core/Core.h"
#include "Core/CoreTiming.h"
@ -14,6 +14,8 @@
#include "Core/PowerPC/JitArm32/JitAsm.h"
#include "Core/PowerPC/JitArm32/JitRegCache.h"
using namespace ArmGen;
void JitArm::ComputeRC(ARMReg value, int cr)
{
ARMReg rB = gpr.GetReg();

4
Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStore.cpp
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@ -3,7 +3,7 @@
// Refer to the license.txt file included.
#include "Common/ArmEmitter.h"
#include "Common/Common.h"
#include "Common/CommonTypes.h"
#include "Core/ConfigManager.h"
#include "Core/Core.h"
@ -16,6 +16,8 @@
#include "Core/PowerPC/JitArm32/JitAsm.h"
#include "Core/PowerPC/JitArm32/JitRegCache.h"
using namespace ArmGen;
void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset)
{
// All this gets replaced on backpatch

4
Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
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@ -3,7 +3,7 @@
// Refer to the license.txt file included.
#include "Common/ArmEmitter.h"
#include "Common/Common.h"
#include "Common/CommonTypes.h"
#include "Core/ConfigManager.h"
#include "Core/Core.h"
@ -17,6 +17,8 @@
#include "Core/PowerPC/JitArm32/JitFPRCache.h"
#include "Core/PowerPC/JitArm32/JitRegCache.h"
using namespace ArmGen;
void JitArm::lfXX(UGeckoInstruction inst)
{
INSTRUCTION_START

4
Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStorePaired.cpp
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@ -3,7 +3,7 @@
// Refer to the license.txt file included.
#include "Common/ArmEmitter.h"
#include "Common/Common.h"
#include "Common/CommonTypes.h"
#include "Core/Core.h"
#include "Core/CoreTiming.h"
@ -14,6 +14,8 @@
#include "Core/PowerPC/JitArm32/JitAsm.h"
#include "Core/PowerPC/JitArm32/JitRegCache.h"
using namespace ArmGen;
void JitArm::psq_l(UGeckoInstruction inst)
{
INSTRUCTION_START

4
Source/Core/Core/PowerPC/JitArm32/JitArm_Paired.cpp
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@ -3,7 +3,7 @@
// Refer to the license.txt file included.
#include "Common/ArmEmitter.h"
#include "Common/Common.h"
#include "Common/CommonTypes.h"
#include "Core/Core.h"
#include "Core/CoreTiming.h"
@ -15,6 +15,8 @@
#include "Core/PowerPC/JitArm32/JitAsm.h"
#include "Core/PowerPC/JitArm32/JitRegCache.h"
using namespace ArmGen;
void JitArm::ps_rsqrte(UGeckoInstruction inst)
{
INSTRUCTION_START

4
Source/Core/Core/PowerPC/JitArm32/JitArm_SystemRegisters.cpp
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@ -3,7 +3,7 @@
// Refer to the license.txt file included.
#include "Common/ArmEmitter.h"
#include "Common/Common.h"
#include "Common/CommonTypes.h"
#include "Core/Core.h"
#include "Core/CoreTiming.h"
@ -14,6 +14,8 @@
#include "Core/PowerPC/JitArm32/JitAsm.h"
#include "Core/PowerPC/JitArm32/JitRegCache.h"
using namespace ArmGen;
FixupBranch JitArm::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
{
ARMReg RA = gpr.GetReg();

2
Source/Core/Core/PowerPC/JitArm32/JitFPRCache.cpp
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@ -5,6 +5,8 @@
#include "Core/PowerPC/JitArm32/Jit.h"
#include "Core/PowerPC/JitArm32/JitFPRCache.h"
using namespace ArmGen;
ArmFPRCache::ArmFPRCache()
{
emit = 0;

21
Source/Core/Core/PowerPC/JitArm32/JitFPRCache.h
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@ -10,7 +10,6 @@
#include "Core/PowerPC/JitArm32/JitRegCache.h"
#define ARMFPUREGS 32
using namespace ArmGen;
class ArmFPRCache
{
@ -22,28 +21,28 @@ private:
int NUMPPCREG;
int NUMARMREG;
ARMReg *GetAllocationOrder(int &count);
ARMReg *GetPPCAllocationOrder(int &count);
ArmGen::ARMReg *GetAllocationOrder(int &count);
ArmGen::ARMReg *GetPPCAllocationOrder(int &count);
ARMReg GetPPCReg(u32 preg, bool PS1, bool preLoad);
ArmGen::ARMReg GetPPCReg(u32 preg, bool PS1, bool preLoad);
u32 GetLeastUsedRegister(bool increment);
bool FindFreeRegister(u32 &regindex);
protected:
ARMXEmitter *emit;
ArmGen::ARMXEmitter *emit;
public:
ArmFPRCache();
~ArmFPRCache() {}
void Init(ARMXEmitter *emitter);
void Init(ArmGen::ARMXEmitter *emitter);
void Start(PPCAnalyst::BlockRegStats &stats);
void SetEmitter(ARMXEmitter *emitter) {emit = emitter;}
void SetEmitter(ArmGen::ARMXEmitter *emitter) {emit = emitter;}
ARMReg GetReg(bool AutoLock = true); // Return a ARM register we can use.
void Unlock(ARMReg V0);
ArmGen::ARMReg GetReg(bool AutoLock = true); // Return a ARM register we can use.
void Unlock(ArmGen::ARMReg V0);
void Flush(FlushMode mode = FLUSH_ALL);
ARMReg R0(u32 preg, bool preLoad = true); // Returns a cached register
ARMReg R1(u32 preg, bool preLoad = true);
ArmGen::ARMReg R0(u32 preg, bool preLoad = true); // Returns a cached register
ArmGen::ARMReg R1(u32 preg, bool preLoad = true);
};

2
Source/Core/Core/PowerPC/JitArm32/JitRegCache.cpp
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@ -5,6 +5,8 @@
#include "Core/PowerPC/JitArm32/Jit.h"
#include "Core/PowerPC/JitArm32/JitRegCache.h"
using namespace ArmGen;
ArmRegCache::ArmRegCache()
{
emit = 0;

21
Source/Core/Core/PowerPC/JitArm32/JitRegCache.h
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@ -8,7 +8,6 @@
#include "Core/PowerPC/Gekko.h"
#include "Core/PowerPC/PPCAnalyst.h"
using namespace ArmGen;
// This ARM Register cache actually pre loads the most used registers before
// the block to increase speed since every memory load requires two
// instructions to load it. We are going to use R0-RMAX as registers for the
@ -88,12 +87,12 @@ struct JRCPPC
{
u32 PPCReg; // Tied to which PPC Register
bool PS1;
ARMReg Reg; // Tied to which ARM Register
ArmGen::ARMReg Reg; // Tied to which ARM Register
u32 LastLoad;
};
struct JRCReg
{
ARMReg Reg; // Which reg this is.
ArmGen::ARMReg Reg; // Which reg this is.
bool free;
};
class ArmRegCache
@ -106,27 +105,27 @@ private:
int NUMPPCREG;
int NUMARMREG;
ARMReg *GetAllocationOrder(int &count);
ARMReg *GetPPCAllocationOrder(int &count);
ArmGen::ARMReg *GetAllocationOrder(int &count);
ArmGen::ARMReg *GetPPCAllocationOrder(int &count);
u32 GetLeastUsedRegister(bool increment);
bool FindFreeRegister(u32 &regindex);
protected:
ARMXEmitter *emit;
ArmGen::ARMXEmitter *emit;
public:
ArmRegCache();
~ArmRegCache() {}
void Init(ARMXEmitter *emitter);
void Init(ArmGen::ARMXEmitter *emitter);
void Start(PPCAnalyst::BlockRegStats &stats);
ARMReg GetReg(bool AutoLock = true); // Return a ARM register we can use.
void Unlock(ARMReg R0, ARMReg R1 = INVALID_REG, ARMReg R2 = INVALID_REG, ARMReg R3 = INVALID_REG);
ArmGen::ARMReg GetReg(bool AutoLock = true); // Return a ARM register we can use.
void Unlock(ArmGen::ARMReg R0, ArmGen::ARMReg R1 = ArmGen::INVALID_REG, ArmGen::ARMReg R2 = ArmGen::INVALID_REG, ArmGen::ARMReg R3 = ArmGen::INVALID_REG);
void Flush(FlushMode mode = FLUSH_ALL);
ARMReg R(u32 preg); // Returns a cached register
ArmGen::ARMReg R(u32 preg); // Returns a cached register
bool IsImm(u32 preg) { return regs[preg].GetType() == REG_IMM; }
u32 GetImm(u32 preg) { return regs[preg].GetImm(); }
void SetImmediate(u32 preg, u32 imm);
ARMReg BindToRegister(u32 preg);
ArmGen::ARMReg BindToRegister(u32 preg);
};