DSP: Fix the predscale update logic
When the current address is xxxxxxxf, after doing the standard ADPCM decoding and incrementing the current address as usual to get the next address, the DSP will update the predscale register by reading 2 bytes from memory, and add two to get the next address. This means xxxxxx10 cannot be a current address, as the DSP goes from 0f to 12 directly. A more serious issue with the old code is that if the start address is 16-byte aligned, some samples will always be skipped, even when that should not be the case. An easy way to test whether this behaviour is correct is to check the current address register and the predscale after each read. Old code: ... ACCA=00000002, predscale=<value> ACCA=00000003, predscale=<value> ... ACCA=0000000f, predscale=<value> ACCA=00000010, predscale=<another value> ACCA=00000013, predscale=<another value> ACCA=00000014, predscale=<another value> ... New code (and console): ... ACCA=00000002, predscale=<value> ACCA=00000003, predscale=<value> ... ACCA=0000000f, predscale=<value> ACCA=00000012, predscale=<another value> ACCA=00000013, predscale=<another value> ...
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@ -73,13 +73,6 @@ u16 Accelerator::Read(s16* coefs)
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{
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case 0x00: // ADPCM audio
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{
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// ADPCM decoding, not much to explain here.
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if ((m_current_address & 15) == 0)
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{
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m_pred_scale = ReadMemory((m_current_address & ~15) >> 1);
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m_current_address += 2;
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}
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switch (m_end_address & 15)
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{
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case 0: // Tom and Jerry
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@ -111,6 +104,13 @@ u16 Accelerator::Read(s16* coefs)
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m_yn2 = m_yn1;
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m_yn1 = val;
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m_current_address += 1;
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if ((m_current_address & 15) == 0)
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{
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m_pred_scale = ReadMemory((m_current_address & ~15) >> 1);
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m_current_address += 2;
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step_size_bytes += 2;
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}
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break;
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}
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case 0x0A: // 16-bit PCM audio
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