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Memmap: clean up function argument names. 

To be more consistent overall.
This commit is contained in:
Fiora 2015-01-03 10:22:36 -08:00
parent 3d2492627f
commit 821db9798c
3 changed files with 100 additions and 100 deletions
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78
Source/Core/Core/HW/Memmap.cpp
View File

@ -188,9 +188,9 @@ bool AreMemoryBreakpointsActivated()
#endif
}
u32 Read_Instruction(const u32 em_address)
u32 Read_Instruction(const u32 address)
{
UGeckoInstruction inst = ReadUnchecked_U32(em_address);
UGeckoInstruction inst = ReadUnchecked_U32(address);
return inst.hex;
}
@ -235,48 +235,48 @@ void Memset(const u32 _Address, const u8 _iValue, const u32 _iLength)
}
}
void ClearCacheLine(const u32 _Address)
void ClearCacheLine(const u32 address)
{
// FIXME: does this do the right thing if dcbz is run on hardware memory, e.g.
// the FIFO? Do games even do that? Probably not, but we should try to be correct...
for (u32 i = 0; i < 32; i += 8)
Write_U64(0, _Address + i);
Write_U64(0, address + i);
}
void DMA_LCToMemory(const u32 _MemAddr, const u32 _CacheAddr, const u32 _iNumBlocks)
void DMA_LCToMemory(const u32 memAddr, const u32 cacheAddr, const u32 numBlocks)
{
const u8* src = m_pL1Cache + (_CacheAddr & 0x3FFFF);
u8* dst = GetPointer(_MemAddr);
const u8* src = m_pL1Cache + (cacheAddr & 0x3FFFF);
u8* dst = GetPointer(memAddr);
if ((dst != nullptr) && (src != nullptr) && (_MemAddr & 3) == 0 && (_CacheAddr & 3) == 0)
if ((dst != nullptr) && (src != nullptr) && (memAddr & 3) == 0 && (cacheAddr & 3) == 0)
{
memcpy(dst, src, 32 * _iNumBlocks);
memcpy(dst, src, 32 * numBlocks);
}
else
{
for (u32 i = 0; i < 32 * _iNumBlocks; i++)
for (u32 i = 0; i < 32 * numBlocks; i++)
{
u8 Temp = Read_U8(_CacheAddr + i);
Write_U8(Temp, _MemAddr + i);
u8 Temp = Read_U8(cacheAddr + i);
Write_U8(Temp, memAddr + i);
}
}
}
void DMA_MemoryToLC(const u32 _CacheAddr, const u32 _MemAddr, const u32 _iNumBlocks)
void DMA_MemoryToLC(const u32 cacheAddr, const u32 memAddr, const u32 numBlocks)
{
const u8* src = GetPointer(_MemAddr);
u8* dst = m_pL1Cache + (_CacheAddr & 0x3FFFF);
const u8* src = GetPointer(memAddr);
u8* dst = m_pL1Cache + (cacheAddr & 0x3FFFF);
if ((dst != nullptr) && (src != nullptr) && (_MemAddr & 3) == 0 && (_CacheAddr & 3) == 0)
if ((dst != nullptr) && (src != nullptr) && (memAddr & 3) == 0 && (cacheAddr & 3) == 0)
{
memcpy(dst, src, 32 * _iNumBlocks);
memcpy(dst, src, 32 * numBlocks);
}
else
{
for (u32 i = 0; i < 32 * _iNumBlocks; i++)
for (u32 i = 0; i < 32 * numBlocks; i++)
{
u8 Temp = Read_U8(_MemAddr + i);
Write_U8(Temp, _CacheAddr + i);
u8 Temp = Read_U8(memAddr + i);
Write_U8(Temp, cacheAddr + i);
}
}
}
@ -301,16 +301,16 @@ std::string GetString(u32 em_address, size_t size)
// GetPointer must always return an address in the bottom 32 bits of address space, so that 64-bit
// programs don't have problems directly addressing any part of memory.
// TODO re-think with respect to other BAT setups...
u8* GetPointer(const u32 _Address)
u8* GetPointer(const u32 address)
{
switch (_Address >> 28)
switch (address >> 28)
{
case 0x0:
case 0x8:
if ((_Address & 0xfffffff) < REALRAM_SIZE)
return m_pRAM + (_Address & RAM_MASK);
if ((address & 0xfffffff) < REALRAM_SIZE)
return m_pRAM + (address & RAM_MASK);
case 0xc:
switch (_Address >> 24)
switch (address >> 24)
{
case 0xcc:
case 0xcd:
@ -320,8 +320,8 @@ u8* GetPointer(const u32 _Address)
break;
default:
if ((_Address & 0xfffffff) < REALRAM_SIZE)
return m_pRAM + (_Address & RAM_MASK);
if ((address & 0xfffffff) < REALRAM_SIZE)
return m_pRAM + (address & RAM_MASK);
}
case 0x1:
@ -329,53 +329,53 @@ u8* GetPointer(const u32 _Address)
case 0xd:
if (SConfig::GetInstance().m_LocalCoreStartupParameter.bWii)
{
if ((_Address & 0xfffffff) < EXRAM_SIZE)
return m_pEXRAM + (_Address & EXRAM_MASK);
if ((address & 0xfffffff) < EXRAM_SIZE)
return m_pEXRAM + (address & EXRAM_MASK);
}
else
break;
case 0xe:
if (_Address < (0xE0000000 + L1_CACHE_SIZE))
return m_pL1Cache + (_Address & L1_CACHE_MASK);
if (address < (0xE0000000 + L1_CACHE_SIZE))
return m_pL1Cache + (address & L1_CACHE_MASK);
else
break;
default:
if (bFakeVMEM)
return m_pFakeVMEM + (_Address & FAKEVMEM_MASK);
return m_pFakeVMEM + (address & FAKEVMEM_MASK);
}
ERROR_LOG(MEMMAP, "Unknown Pointer %#8x PC %#8x LR %#8x", _Address, PC, LR);
ERROR_LOG(MEMMAP, "Unknown Pointer %#8x PC %#8x LR %#8x", address, PC, LR);
return nullptr;
}
bool IsRAMAddress(const u32 addr, bool allow_locked_cache, bool allow_fake_vmem)
bool IsRAMAddress(const u32 address, bool allow_locked_cache, bool allow_fake_vmem)
{
switch ((addr >> 24) & 0xFC)
switch ((address >> 24) & 0xFC)
{
case 0x00:
case 0x80:
case 0xC0:
if ((addr & 0x1FFFFFFF) < RAM_SIZE)
if ((address & 0x1FFFFFFF) < RAM_SIZE)
return true;
else
return false;
case 0x10:
case 0x90:
case 0xD0:
if (SConfig::GetInstance().m_LocalCoreStartupParameter.bWii && (addr & 0x0FFFFFFF) < EXRAM_SIZE)
if (SConfig::GetInstance().m_LocalCoreStartupParameter.bWii && (address & 0x0FFFFFFF) < EXRAM_SIZE)
return true;
else
return false;
case 0xE0:
if (allow_locked_cache && addr - 0xE0000000 < L1_CACHE_SIZE)
if (allow_locked_cache && address - 0xE0000000 < L1_CACHE_SIZE)
return true;
else
return false;
case 0x7C:
if (allow_fake_vmem && bFakeVMEM && addr >= 0x7E000000)
if (allow_fake_vmem && bFakeVMEM && address >= 0x7E000000)
return true;
else
return false;

28
Source/Core/Core/HW/Memmap.h
View File

@ -74,19 +74,19 @@ void Clear();
bool AreMemoryBreakpointsActivated();
// ONLY for use by GUI
u8 ReadUnchecked_U8(const u32 _Address);
u32 ReadUnchecked_U32(const u32 _Address);
u8 ReadUnchecked_U8(const u32 address);
u32 ReadUnchecked_U32(const u32 address);
void WriteUnchecked_U8(const u8 _Data, const u32 _Address);
void WriteUnchecked_U32(const u32 _Data, const u32 _Address);
void WriteUnchecked_U8(const u8 var, const u32 address);
void WriteUnchecked_U32(const u32 var, const u32 address);
bool IsRAMAddress(const u32 addr, bool allow_locked_cache = false, bool allow_fake_vmem = false);
bool IsRAMAddress(const u32 address, bool allow_locked_cache = false, bool allow_fake_vmem = false);
// used by interpreter to read instructions, uses iCache
u32 Read_Opcode(const u32 _Address);
u32 Read_Opcode(const u32 address);
// this is used by Debugger a lot.
// For now, just reads from memory!
u32 Read_Instruction(const u32 _Address);
u32 Read_Instruction(const u32 address);
// For use by emulator
@ -118,13 +118,13 @@ void Write_F64(const double var, const u32 address);
std::string GetString(u32 em_address, size_t size = 0);
u8* GetPointer(const u32 _Address);
void DMA_LCToMemory(const u32 _iMemAddr, const u32 _iCacheAddr, const u32 _iNumBlocks);
void DMA_MemoryToLC(const u32 _iCacheAddr, const u32 _iMemAddr, const u32 _iNumBlocks);
u8* GetPointer(const u32 address);
void DMA_LCToMemory(const u32 memAddr, const u32 cacheAddr, const u32 numBlocks);
void DMA_MemoryToLC(const u32 cacheAddr, const u32 memAddr, const u32 numBlocks);
void CopyFromEmu(void* data, u32 address, size_t size);
void CopyToEmu(u32 address, const void* data, size_t size);
void Memset(const u32 _Address, const u8 _Data, const u32 _iLength);
void ClearCacheLine(const u32 _Address); // Zeroes 32 bytes; address should be 32-byte-aligned
void Memset(const u32 address, const u8 var, const u32 length);
void ClearCacheLine(const u32 address); // Zeroes 32 bytes; address should be 32-byte-aligned
// TLB functions
void SDRUpdated();
@ -135,8 +135,8 @@ enum XCheckTLBFlag
FLAG_WRITE,
FLAG_OPCODE,
};
template <const XCheckTLBFlag _Flag> u32 TranslateAddress(const u32 _Address);
void InvalidateTLBEntry(u32 _Address);
template <const XCheckTLBFlag flag> u32 TranslateAddress(const u32 address);
void InvalidateTLBEntry(u32 address);
extern u32 pagetable_base;
extern u32 pagetable_hashmask;
}

94
Source/Core/Core/HW/MemmapFunctions.cpp
View File

@ -284,9 +284,9 @@ __forceinline void WriteToHardware(u32 em_address, const T data)
static void GenerateISIException(u32 effective_address);
u32 Read_Opcode(u32 _Address)
u32 Read_Opcode(u32 address)
{
if (_Address == 0x00000000)
if (address == 0x00000000)
{
// FIXME use assert?
PanicAlert("Program tried to read an opcode from [00000000]. It has crashed.");
@ -294,22 +294,22 @@ u32 Read_Opcode(u32 _Address)
}
if (SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU &&
(_Address & ADDR_MASK_MEM1))
(address & ADDR_MASK_MEM1))
{
// TODO: Check for MSR instruction address translation flag before translating
u32 tlb_addr = TranslateAddress<FLAG_OPCODE>(_Address);
u32 tlb_addr = TranslateAddress<FLAG_OPCODE>(address);
if (tlb_addr == 0)
{
GenerateISIException(_Address);
GenerateISIException(address);
return 0;
}
else
{
_Address = tlb_addr;
address = tlb_addr;
}
}
return PowerPC::ppcState.iCache.ReadInstruction(_Address);
return PowerPC::ppcState.iCache.ReadInstruction(address);
}
static __forceinline void Memcheck(u32 address, u32 var, bool write, int size)
@ -553,21 +553,21 @@ union UPTE2
u32 Hex;
};
static void GenerateDSIException(u32 _EffectiveAddress, bool _bWrite)
static void GenerateDSIException(u32 effectiveAddress, bool write)
{
// DSI exceptions are only supported in MMU mode.
if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU)
{
PanicAlertT("Invalid %s to 0x%08x, PC = 0x%08x ", _bWrite ? "Write to" : "Read from", _EffectiveAddress, PC);
PanicAlertT("Invalid %s to 0x%08x, PC = 0x%08x ", write ? "Write to" : "Read from", effectiveAddress, PC);
return;
}
if (_bWrite)
if (effectiveAddress)
PowerPC::ppcState.spr[SPR_DSISR] = PPC_EXC_DSISR_PAGE | PPC_EXC_DSISR_STORE;
else
PowerPC::ppcState.spr[SPR_DSISR] = PPC_EXC_DSISR_PAGE;
PowerPC::ppcState.spr[SPR_DAR] = _EffectiveAddress;
PowerPC::ppcState.spr[SPR_DAR] = effectiveAddress;
Common::AtomicOr(PowerPC::ppcState.Exceptions, EXCEPTION_DSI);
}
@ -614,14 +614,14 @@ enum TLBLookupResult
TLB_UPDATE_C
};
static __forceinline TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag _Flag, const u32 vpa, u32 *paddr)
static __forceinline TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag flag, const u32 vpa, u32 *paddr)
{
int tag = vpa >> HW_PAGE_INDEX_SHIFT;
PowerPC::tlb_entry *tlbe = &PowerPC::ppcState.tlb[_Flag == FLAG_OPCODE][tag & HW_PAGE_INDEX_MASK];
PowerPC::tlb_entry *tlbe = &PowerPC::ppcState.tlb[flag == FLAG_OPCODE][tag & HW_PAGE_INDEX_MASK];
if (tlbe->tag[0] == tag)
{
// Check if C bit requires updating
if (_Flag == FLAG_WRITE)
if (flag == FLAG_WRITE)
{
UPTE2 PTE2;
PTE2.Hex = tlbe->pte[0];
@ -633,7 +633,7 @@ static __forceinline TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag _F
}
}
if (_Flag != FLAG_NO_EXCEPTION)
if (flag != FLAG_NO_EXCEPTION)
tlbe->recent = 0;
*paddr = tlbe->paddr[0] | (vpa & 0xfff);
@ -643,7 +643,7 @@ static __forceinline TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag _F
if (tlbe->tag[1] == tag)
{
// Check if C bit requires updating
if (_Flag == FLAG_WRITE)
if (flag == FLAG_WRITE)
{
UPTE2 PTE2;
PTE2.Hex = tlbe->pte[1];
@ -655,7 +655,7 @@ static __forceinline TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag _F
}
}
if (_Flag != FLAG_NO_EXCEPTION)
if (flag != FLAG_NO_EXCEPTION)
tlbe->recent = 1;
*paddr = tlbe->paddr[1] | (vpa & 0xfff);
@ -665,13 +665,13 @@ static __forceinline TLBLookupResult LookupTLBPageAddress(const XCheckTLBFlag _F
return TLB_NOTFOUND;
}
static __forceinline void UpdateTLBEntry(const XCheckTLBFlag _Flag, UPTE2 PTE2, const u32 vpa)
static __forceinline void UpdateTLBEntry(const XCheckTLBFlag flag, UPTE2 PTE2, const u32 address)
{
if (_Flag == FLAG_NO_EXCEPTION)
if (flag == FLAG_NO_EXCEPTION)
return;
int tag = vpa >> HW_PAGE_INDEX_SHIFT;
PowerPC::tlb_entry *tlbe = &PowerPC::ppcState.tlb[_Flag == FLAG_OPCODE][tag & HW_PAGE_INDEX_MASK];
int tag = address >> HW_PAGE_INDEX_SHIFT;
PowerPC::tlb_entry *tlbe = &PowerPC::ppcState.tlb[flag == FLAG_OPCODE][tag & HW_PAGE_INDEX_MASK];
int index = tlbe->recent == 0 && tlbe->tag[0] != TLB_TAG_INVALID;
tlbe->recent = index;
tlbe->paddr[index] = PTE2.RPN << HW_PAGE_INDEX_SHIFT;
@ -679,33 +679,33 @@ static __forceinline void UpdateTLBEntry(const XCheckTLBFlag _Flag, UPTE2 PTE2,
tlbe->tag[index] = tag;
}
void InvalidateTLBEntry(u32 vpa)
void InvalidateTLBEntry(u32 address)
{
PowerPC::tlb_entry *tlbe = &PowerPC::ppcState.tlb[0][(vpa >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK];
PowerPC::tlb_entry *tlbe = &PowerPC::ppcState.tlb[0][(address >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK];
tlbe->tag[0] = TLB_TAG_INVALID;
tlbe->tag[1] = TLB_TAG_INVALID;
PowerPC::tlb_entry *tlbe_i = &PowerPC::ppcState.tlb[1][(vpa >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK];
PowerPC::tlb_entry *tlbe_i = &PowerPC::ppcState.tlb[1][(address >> HW_PAGE_INDEX_SHIFT) & HW_PAGE_INDEX_MASK];
tlbe_i->tag[0] = TLB_TAG_INVALID;
tlbe_i->tag[1] = TLB_TAG_INVALID;
}
// Page Address Translation
static __forceinline u32 TranslatePageAddress(const u32 _Address, const XCheckTLBFlag _Flag)
static __forceinline u32 TranslatePageAddress(const u32 address, const XCheckTLBFlag flag)
{
// TLB cache
// This catches 99%+ of lookups in practice, so the actual page table entry code below doesn't benefit
// much from optimization.
u32 translatedAddress = 0;
TLBLookupResult res = LookupTLBPageAddress(_Flag, _Address, &translatedAddress);
TLBLookupResult res = LookupTLBPageAddress(flag , address, &translatedAddress);
if (res == TLB_FOUND)
return translatedAddress;
u32 sr = PowerPC::ppcState.sr[EA_SR(_Address)];
u32 sr = PowerPC::ppcState.sr[EA_SR(address)];
u32 offset = EA_Offset(_Address); // 12 bit
u32 page_index = EA_PageIndex(_Address); // 16 bit
u32 offset = EA_Offset(address); // 12 bit
u32 page_index = EA_PageIndex(address); // 16 bit
u32 VSID = SR_VSID(sr); // 24 bit
u32 api = EA_API(_Address); // 6 bit (part of page_index)
u32 api = EA_API(address); // 6 bit (part of page_index)
// Direct access to the fastmem Arena
// FIXME: is this the best idea for clean code?
@ -734,7 +734,7 @@ static __forceinline u32 TranslatePageAddress(const u32 _Address, const XCheckTL
PTE2.Hex = bswap((*(u32*)&base_mem[(pteg_addr + 4)]));
// set the access bits
switch (_Flag)
switch (flag)
{
case FLAG_NO_EXCEPTION: break;
case FLAG_READ: PTE2.R = 1; break;
@ -742,12 +742,12 @@ static __forceinline u32 TranslatePageAddress(const u32 _Address, const XCheckTL
case FLAG_OPCODE: PTE2.R = 1; break;
}
if (_Flag != FLAG_NO_EXCEPTION)
if (flag != FLAG_NO_EXCEPTION)
*(u32*)&base_mem[(pteg_addr + 4)] = bswap(PTE2.Hex);
// We already updated the TLB entry if this was caused by a C bit.
if (res != TLB_UPDATE_C)
UpdateTLBEntry(_Flag, PTE2, _Address);
UpdateTLBEntry(flag, PTE2, address);
return (PTE2.RPN << 12) | offset;
}
@ -793,7 +793,7 @@ static inline bool CheckAddrBats(const u32 addr, u32* result, u32 batu, u32 spr)
}
// Block Address Translation
static u32 TranslateBlockAddress(const u32 addr, const XCheckTLBFlag _Flag)
static u32 TranslateBlockAddress(const u32 address, const XCheckTLBFlag flag)
{
u32 result = 0;
UReg_MSR& m_MSR = ((UReg_MSR&)PowerPC::ppcState.msr);
@ -802,22 +802,22 @@ static u32 TranslateBlockAddress(const u32 addr, const XCheckTLBFlag _Flag)
// Check for enhanced mode (secondary BAT enable) using 8 BATs
bool enhanced_bats = SConfig::GetInstance().m_LocalCoreStartupParameter.bWii && HID4.SBE;
if (_Flag != FLAG_OPCODE)
if (flag != FLAG_OPCODE)
{
if (!CheckAddrBats(addr, &result, batu, SPR_DBAT0U) && enhanced_bats)
CheckAddrBats(addr, &result, batu, SPR_DBAT4U);
if (!CheckAddrBats(address, &result, batu, SPR_DBAT0U) && enhanced_bats)
CheckAddrBats(address, &result, batu, SPR_DBAT4U);
}
else
{
if (!CheckAddrBats(addr, &result, batu, SPR_IBAT0U) && enhanced_bats)
CheckAddrBats(addr, &result, batu, SPR_IBAT4U);
if (!CheckAddrBats(address, &result, batu, SPR_IBAT0U) && enhanced_bats)
CheckAddrBats(address, &result, batu, SPR_IBAT4U);
}
return result;
}
// Translate effective address using BAT or PAT. Returns 0 if the address cannot be translated.
template <const XCheckTLBFlag _Flag>
u32 TranslateAddress(const u32 _Address)
template <const XCheckTLBFlag flag>
u32 TranslateAddress(const u32 address)
{
// Check MSR[IR] bit before translating instruction addresses. Rogue Leader clears IR and DR??
//if ((_Flag == FLAG_OPCODE) && !(MSR & (1 << (31 - 26)))) return _Address;
@ -829,15 +829,15 @@ u32 TranslateAddress(const u32 _Address)
// so only do it where it's really needed.
if (SConfig::GetInstance().m_LocalCoreStartupParameter.bBAT)
{
u32 tlb_addr = TranslateBlockAddress(_Address, _Flag);
u32 tlb_addr = TranslateBlockAddress(address, flag);
if (tlb_addr)
return tlb_addr;
}
return TranslatePageAddress(_Address, _Flag);
return TranslatePageAddress(address, flag);
}
template u32 TranslateAddress<Memory::FLAG_NO_EXCEPTION>(const u32 _Address);
template u32 TranslateAddress<Memory::FLAG_READ>(const u32 _Address);
template u32 TranslateAddress<Memory::FLAG_WRITE>(const u32 _Address);
template u32 TranslateAddress<Memory::FLAG_OPCODE>(const u32 _Address);
template u32 TranslateAddress<Memory::FLAG_NO_EXCEPTION>(const u32 address);
template u32 TranslateAddress<Memory::FLAG_READ>(const u32 address);
template u32 TranslateAddress<Memory::FLAG_WRITE>(const u32 address);
template u32 TranslateAddress<Memory::FLAG_OPCODE>(const u32 address);
} // namespace