ShuriZma
/
dolphin
mirror of https://github.com/dolphin-emu/dolphin.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

JitArm64: Move ps instructions from fp_arith to ps_arith 

This lets us simplify fp_arith without making ps_arith much more
complicated.

No behavior change.
This commit is contained in:
JosJuice 2022-10-09 12:31:29 +02:00
parent 554a2fd332
commit 812067ab7c
3 changed files with 94 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

198
Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
View File

@ -69,154 +69,102 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
u32 op5 = inst.SUBOP5;
bool single = inst.OPCD == 59;
bool packed = inst.OPCD == 4;
const bool use_c = op5 >= 25; // fmul and all kind of fmaddXX
const bool use_b = op5 != 25; // fmul uses no B
const bool outputs_are_singles = single || packed;
const bool round_c = use_c && outputs_are_singles && !js.op->fprIsSingle[inst.FC];
const bool output_is_single = inst.OPCD == 59;
const bool inaccurate_fma = op5 > 25 && !Config::Get(Config::SESSION_USE_FMA);
const bool round_c = use_c && output_is_single && !js.op->fprIsSingle[inst.FC];
const auto inputs_are_singles_func = [&] {
return fpr.IsSingle(a, !packed) && (!use_b || fpr.IsSingle(b, !packed)) &&
(!use_c || fpr.IsSingle(c, !packed));
return fpr.IsSingle(a, true) && (!use_b || fpr.IsSingle(b, true)) &&
(!use_c || fpr.IsSingle(c, true));
};
const bool inputs_are_singles = inputs_are_singles_func();
ARM64Reg VA{}, VB{}, VC{}, VD{};
const RegType type =
(inputs_are_singles && output_is_single) ? RegType::LowerPairSingle : RegType::LowerPair;
const RegType type_out =
output_is_single ? (inputs_are_singles ? RegType::DuplicatedSingle : RegType::Duplicated) :
RegType::LowerPair;
const auto reg_encoder =
(inputs_are_singles && output_is_single) ? EncodeRegToSingle : EncodeRegToDouble;
const ARM64Reg VA = reg_encoder(fpr.R(a, type));
const ARM64Reg VB = use_b ? reg_encoder(fpr.R(b, type)) : ARM64Reg::INVALID_REG;
ARM64Reg VC = use_c ? reg_encoder(fpr.R(c, type)) : ARM64Reg::INVALID_REG;
const ARM64Reg VD = reg_encoder(fpr.RW(d, type_out));
ARM64Reg V0Q = ARM64Reg::INVALID_REG;
ARM64Reg V1Q = ARM64Reg::INVALID_REG;
if (packed)
if (round_c)
{
const RegType type = inputs_are_singles ? RegType::Single : RegType::Register;
const u8 size = inputs_are_singles ? 32 : 64;
const auto reg_encoder = inputs_are_singles ? EncodeRegToDouble : EncodeRegToQuad;
ASSERT_MSG(DYNA_REC, !inputs_are_singles, "Tried to apply 25-bit precision to single");
VA = reg_encoder(fpr.R(a, type));
if (use_b)
VB = reg_encoder(fpr.R(b, type));
if (use_c)
VC = reg_encoder(fpr.R(c, type));
VD = reg_encoder(fpr.RW(d, type));
V1Q = fpr.GetReg();
if (round_c)
{
ASSERT_MSG(DYNA_REC, !inputs_are_singles, "Tried to apply 25-bit precision to single");
V0Q = fpr.GetReg();
Force25BitPrecision(reg_encoder(V0Q), VC);
VC = reg_encoder(V0Q);
}
switch (op5)
{
case 18:
m_float_emit.FDIV(size, VD, VA, VB);
break;
case 20:
m_float_emit.FSUB(size, VD, VA, VB);
break;
case 21:
m_float_emit.FADD(size, VD, VA, VB);
break;
case 25:
m_float_emit.FMUL(size, VD, VA, VC);
break;
default:
ASSERT_MSG(DYNA_REC, 0, "fp_arith");
break;
}
Force25BitPrecision(reg_encoder(V1Q), VC);
VC = reg_encoder(V1Q);
}
else
ARM64Reg inaccurate_fma_temp_reg = VD;
if (inaccurate_fma && d == b)
{
const RegType type =
(inputs_are_singles && single) ? RegType::LowerPairSingle : RegType::LowerPair;
const RegType type_out =
single ? (inputs_are_singles ? RegType::DuplicatedSingle : RegType::Duplicated) :
RegType::LowerPair;
const auto reg_encoder = (inputs_are_singles && single) ? EncodeRegToSingle : EncodeRegToDouble;
V0Q = fpr.GetReg();
VA = reg_encoder(fpr.R(a, type));
if (use_b)
VB = reg_encoder(fpr.R(b, type));
if (use_c)
VC = reg_encoder(fpr.R(c, type));
VD = reg_encoder(fpr.RW(d, type_out));
inaccurate_fma_temp_reg = reg_encoder(V0Q);
}
const bool inaccurate_fma = op5 > 25 && !Config::Get(Config::SESSION_USE_FMA);
if (round_c)
switch (op5)
{
case 18:
m_float_emit.FDIV(VD, VA, VB);
break;
case 20:
m_float_emit.FSUB(VD, VA, VB);
break;
case 21:
m_float_emit.FADD(VD, VA, VB);
break;
case 25:
m_float_emit.FMUL(VD, VA, VC);
break;
// While it may seem like PowerPC's nmadd/nmsub map to AArch64's nmadd/msub [sic],
// the subtly different definitions affect how signed zeroes are handled.
// Also, PowerPC's nmadd/nmsub perform rounding before the final negation.
// So, we negate using a separate FNEG instruction instead of using AArch64's nmadd/msub.
case 28: // fmsub: "D = A*C - B" vs "Vd = (-Va) + Vn*Vm"
case 30: // fnmsub: "D = -(A*C - B)" vs "Vd = -((-Va) + Vn*Vm)"
if (inaccurate_fma)
{
ASSERT_MSG(DYNA_REC, !inputs_are_singles, "Tried to apply 25-bit precision to single");
V1Q = fpr.GetReg();
Force25BitPrecision(reg_encoder(V1Q), VC);
VC = reg_encoder(V1Q);
m_float_emit.FMUL(inaccurate_fma_temp_reg, VA, VC);
m_float_emit.FSUB(VD, inaccurate_fma_temp_reg, VB);
}
ARM64Reg inaccurate_fma_temp_reg = VD;
if (inaccurate_fma && d == b)
else
{
V0Q = fpr.GetReg();
inaccurate_fma_temp_reg = reg_encoder(V0Q);
m_float_emit.FNMSUB(VD, VA, VC, VB);
}
switch (op5)
if (op5 == 30)
m_float_emit.FNEG(VD, VD);
break;
case 29: // fmadd: "D = A*C + B" vs "Vd = Va + Vn*Vm"
case 31: // fnmadd: "D = -(A*C + B)" vs "Vd = -(Va + Vn*Vm)"
if (inaccurate_fma)
{
case 18:
m_float_emit.FDIV(VD, VA, VB);
break;
case 20:
m_float_emit.FSUB(VD, VA, VB);
break;
case 21:
m_float_emit.FADD(VD, VA, VB);
break;
case 25:
m_float_emit.FMUL(VD, VA, VC);
break;
// While it may seem like PowerPC's nmadd/nmsub map to AArch64's nmadd/msub [sic],
// the subtly different definitions affect how signed zeroes are handled.
// Also, PowerPC's nmadd/nmsub perform rounding before the final negation.
// So, we negate using a separate FNEG instruction instead of using AArch64's nmadd/msub.
case 28: // fmsub: "D = A*C - B" vs "Vd = (-Va) + Vn*Vm"
case 30: // fnmsub: "D = -(A*C - B)" vs "Vd = -((-Va) + Vn*Vm)"
if (inaccurate_fma)
{
m_float_emit.FMUL(inaccurate_fma_temp_reg, VA, VC);
m_float_emit.FSUB(VD, inaccurate_fma_temp_reg, VB);
}
else
{
m_float_emit.FNMSUB(VD, VA, VC, VB);
}
if (op5 == 30)
m_float_emit.FNEG(VD, VD);
break;
case 29: // fmadd: "D = A*C + B" vs "Vd = Va + Vn*Vm"
case 31: // fnmadd: "D = -(A*C + B)" vs "Vd = -(Va + Vn*Vm)"
if (inaccurate_fma)
{
m_float_emit.FMUL(inaccurate_fma_temp_reg, VA, VC);
m_float_emit.FADD(VD, inaccurate_fma_temp_reg, VB);
}
else
{
m_float_emit.FMADD(VD, VA, VC, VB);
}
if (op5 == 31)
m_float_emit.FNEG(VD, VD);
break;
default:
ASSERT_MSG(DYNA_REC, 0, "fp_arith");
break;
m_float_emit.FMUL(inaccurate_fma_temp_reg, VA, VC);
m_float_emit.FADD(VD, inaccurate_fma_temp_reg, VB);
}
else
{
m_float_emit.FMADD(VD, VA, VC, VB);
}
if (op5 == 31)
m_float_emit.FNEG(VD, VD);
break;
default:
ASSERT_MSG(DYNA_REC, 0, "fp_arith");
break;
}
if (V0Q != ARM64Reg::INVALID_REG)
@ -224,7 +172,7 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
if (V1Q != ARM64Reg::INVALID_REG)
fpr.Unlock(V1Q);
if (outputs_are_singles)
if (output_is_single)
{
ASSERT_MSG(DYNA_REC, inputs_are_singles == inputs_are_singles_func(),
"Register allocation turned singles into doubles in the middle of fp_arith");
@ -232,7 +180,7 @@ void JitArm64::fp_arith(UGeckoInstruction inst)
fpr.FixSinglePrecision(d);
}
SetFPRFIfNeeded(outputs_are_singles, VD);
SetFPRFIfNeeded(output_is_single, VD);
}
void JitArm64::fp_logic(UGeckoInstruction inst)

21
Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
View File

@ -86,22 +86,23 @@ void JitArm64::ps_arith(UGeckoInstruction inst)
const u32 d = inst.FD;
const u32 op5 = inst.SUBOP5;
const bool use_b = (op5 & ~0x1) != 12; // muls uses no B
const bool use_c = op5 == 25 || (op5 & ~0x13) == 12; // mul, muls, and all kinds of maddXX
const bool use_b = op5 != 25 && (op5 & ~0x1) != 12; // mul and muls don't use B
const auto singles_func = [&] {
return fpr.IsSingle(a) && (!use_b || fpr.IsSingle(b)) && fpr.IsSingle(c);
return fpr.IsSingle(a) && (!use_b || fpr.IsSingle(b)) && (!use_c || fpr.IsSingle(c));
};
const bool singles = singles_func();
const bool inaccurate_fma = !Config::Get(Config::SESSION_USE_FMA);
const bool round_c = !js.op->fprIsSingle[inst.FC];
const bool round_c = use_c && !js.op->fprIsSingle[inst.FC];
const RegType type = singles ? RegType::Single : RegType::Register;
const u8 size = singles ? 32 : 64;
const auto reg_encoder = singles ? EncodeRegToDouble : EncodeRegToQuad;
const ARM64Reg VA = reg_encoder(fpr.R(a, type));
const ARM64Reg VB = use_b ? reg_encoder(fpr.R(b, type)) : ARM64Reg::INVALID_REG;
ARM64Reg VC = reg_encoder(fpr.R(c, type));
ARM64Reg VC = use_c ? reg_encoder(fpr.R(c, type)) : ARM64Reg::INVALID_REG;
const ARM64Reg VD = reg_encoder(fpr.RW(d, type));
ARM64Reg V0Q = ARM64Reg::INVALID_REG;
@ -188,6 +189,18 @@ void JitArm64::ps_arith(UGeckoInstruction inst)
result_reg = V0;
}
break;
case 18: // ps_div
m_float_emit.FDIV(size, VD, VA, VB);
break;
case 20: // ps_sub
m_float_emit.FSUB(size, VD, VA, VB);
break;
case 21: // ps_add
m_float_emit.FADD(size, VD, VA, VB);
break;
case 25: // ps_mul
m_float_emit.FMUL(size, VD, VA, VC);
break;
case 28: // ps_msub: d = a * c - b
case 30: // ps_nmsub: d = -(a * c - b)
if (inaccurate_fma)

8
Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
View File

@ -112,12 +112,12 @@ constexpr std::array<GekkoOPTemplate, 17> table4_2{{
{13, &JitArm64::ps_arith}, // ps_muls1
{14, &JitArm64::ps_arith}, // ps_madds0
{15, &JitArm64::ps_arith}, // ps_madds1
{18, &JitArm64::fp_arith}, // ps_div
{20, &JitArm64::fp_arith}, // ps_sub
{21, &JitArm64::fp_arith}, // ps_add
{18, &JitArm64::ps_arith}, // ps_div
{20, &JitArm64::ps_arith}, // ps_sub
{21, &JitArm64::ps_arith}, // ps_add
{23, &JitArm64::ps_sel}, // ps_sel
{24, &JitArm64::ps_res}, // ps_res
{25, &JitArm64::fp_arith}, // ps_mul
{25, &JitArm64::ps_arith}, // ps_mul
{26, &JitArm64::ps_rsqrte}, // ps_rsqrte
{28, &JitArm64::ps_arith}, // ps_msub
{29, &JitArm64::ps_arith}, // ps_madd