Improve PPCCache lookup table
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9d39647f9e
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811d942222
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@ -168,11 +168,11 @@ void Cache::Invalidate(u32 addr)
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if (valid[set] & (1U << way))
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{
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if (addrs[set][way] & CACHE_VMEM_BIT)
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lookup_table_vmem[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table_vmem[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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else if (addrs[set][way] & CACHE_EXRAM_BIT)
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lookup_table_ex[((addrs[set][way] >> 5) & 0x1fff80) | set] = 0xff;
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lookup_table_ex[(addrs[set][way] >> 5) & 0x1fffff] = 0xff;
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else
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lookup_table[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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valid[set] &= ~(1U << way);
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modified[set] &= ~(1U << way);
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@ -195,11 +195,11 @@ void Cache::Flush(u32 addr)
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memory.CopyToEmu((addr & ~0x1f), reinterpret_cast<u8*>(data[set][way].data()), 32);
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if (addrs[set][way] & CACHE_VMEM_BIT)
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lookup_table_vmem[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table_vmem[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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else if (addrs[set][way] & CACHE_EXRAM_BIT)
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lookup_table_ex[((addrs[set][way] >> 5) & 0x1fff80) | set] = 0xff;
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lookup_table_ex[(addrs[set][way] >> 5) & 0x1fffff] = 0xff;
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else
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lookup_table[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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valid[set] &= ~(1U << way);
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modified[set] &= ~(1U << way);
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@ -249,11 +249,11 @@ std::pair<u32, u32> Cache::GetCache(u32 addr, bool locked)
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memory.CopyToEmu(addrs[set][way], reinterpret_cast<u8*>(data[set][way].data()), 32);
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if (addrs[set][way] & CACHE_VMEM_BIT)
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lookup_table_vmem[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table_vmem[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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else if (addrs[set][way] & CACHE_EXRAM_BIT)
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lookup_table_ex[((addrs[set][way] >> 5) & 0x1fff80) | set] = 0xff;
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lookup_table_ex[(addrs[set][way] >> 5) & 0x1fffff] = 0xff;
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else
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lookup_table[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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}
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// load
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@ -265,6 +265,7 @@ std::pair<u32, u32> Cache::GetCache(u32 addr, bool locked)
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lookup_table_ex[(addr >> 5) & 0x1fffff] = way;
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else
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lookup_table[(addr >> 5) & 0xfffff] = way;
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addrs[set][way] = addr;
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valid[set] |= (1 << way);
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modified[set] &= ~(1 << way);
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@ -351,11 +352,11 @@ void Cache::DoState(PointerWrap& p)
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if ((valid[set] & (1 << way)) != 0)
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{
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if (addrs[set][way] & CACHE_VMEM_BIT)
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lookup_table_vmem[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table_vmem[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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else if (addrs[set][way] & CACHE_EXRAM_BIT)
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lookup_table_ex[((addrs[set][way] >> 5) & 0x1fff80) | set] = 0xff;
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lookup_table_ex[(addrs[set][way] >> 5) & 0x1fffff] = 0xff;
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else
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lookup_table[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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}
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}
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}
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@ -377,11 +378,11 @@ void Cache::DoState(PointerWrap& p)
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if ((valid[set] & (1 << way)) != 0)
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{
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if (addrs[set][way] & CACHE_VMEM_BIT)
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lookup_table_vmem[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table_vmem[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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else if (addrs[set][way] & CACHE_EXRAM_BIT)
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lookup_table_ex[((addrs[set][way] >> 5) & 0x1fff80) | set] = 0xff;
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lookup_table_ex[(addrs[set][way] >> 5) & 0x1fffff] = 0xff;
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else
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lookup_table[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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}
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}
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}
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@ -413,11 +414,11 @@ void InstructionCache::Invalidate(u32 addr)
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if (valid[set] & (1U << way))
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{
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if (addrs[set][way] & CACHE_VMEM_BIT)
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lookup_table_vmem[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table_vmem[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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else if (addrs[set][way] & CACHE_EXRAM_BIT)
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lookup_table_ex[((addrs[set][way] >> 5) & 0x1fff80) | set] = 0xff;
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lookup_table_ex[(addrs[set][way] >> 5) & 0x1fffff] = 0xff;
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else
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lookup_table[((addrs[set][way] >> 5) & 0xfff80) | set] = 0xff;
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lookup_table[(addrs[set][way] >> 5) & 0xfffff] = 0xff;
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}
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}
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valid[set] = 0;
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@ -23,7 +23,13 @@ constexpr u32 CACHE_VMEM_BIT = 0x20000000;
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struct Cache
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{
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std::array<std::array<std::array<u32, CACHE_BLOCK_SIZE>, CACHE_WAYS>, CACHE_SETS> data{};
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// Stores the 32-byte aligned address of the start of each cache block. This consists of the cache
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// set and tag. Real hardware only needs to store the tag, but also including the set simplifies
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// debugging and getting the actual address in the cache, without changing behavior (as the set
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// portion of the address is by definition the same for all addresses in a set).
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std::array<std::array<u32, CACHE_WAYS>, CACHE_SETS> addrs{};
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std::array<u32, CACHE_SETS> plru{};
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std::array<u32, CACHE_SETS> valid{};
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std::array<u32, CACHE_SETS> modified{};
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