Improve Atomic.h:
- For GCC, use intrinsics that will work on ARM. - Add AtomicExchangeAcquire. - Make Atomic{Load,LoadAcquire,Store,StoreRelease} work for any suitable type.
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@ -40,27 +40,45 @@ inline void AtomicIncrement(volatile u32& target) {
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__sync_add_and_fetch(&target, 1);
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}
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inline u32 AtomicLoad(volatile u32& src) {
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return src; // 32-bit reads are always atomic.
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}
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inline u32 AtomicLoadAcquire(volatile u32& src) {
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//keep the compiler from caching any memory references
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u32 result = src; // 32-bit reads are always atomic.
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//__sync_synchronize(); // TODO: May not be necessary.
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// Compiler instruction only. x86 loads always have acquire semantics.
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__asm__ __volatile__ ( "":::"memory" );
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return result;
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}
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inline void AtomicOr(volatile u32& target, u32 value) {
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__sync_or_and_fetch(&target, value);
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}
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inline void AtomicStore(volatile u32& dest, u32 value) {
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dest = value; // 32-bit writes are always atomic.
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#ifdef __clang__
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template <typename T>
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_Atomic(T)* ToC11Atomic(volatile T* loc)
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{
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return (_Atomic(T)*) loc;
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}
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inline void AtomicStoreRelease(volatile u32& dest, u32 value) {
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__sync_lock_test_and_set(&dest, value); // TODO: Wrong! This function is has acquire semantics.
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#define __atomic_load_n(p, m) __c11_atomic_load(ToC11Atomic(p), m)
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#define __atomic_store_n(p, v, m) __c11_atomic_store(ToC11Atomic(p), v, m)
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#define __atomic_exchange_n(p, v, m) __c11_atomic_exchange(ToC11Atomic(p), v, m)
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#endif
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template <typename T>
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inline T AtomicLoad(volatile T& src) {
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return __atomic_load_n(&src, __ATOMIC_RELAXED);
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}
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template <typename T>
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inline T AtomicLoadAcquire(volatile T& src) {
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return __atomic_load_n(&src, __ATOMIC_ACQUIRE);
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}
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template <typename T, typename U>
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inline void AtomicStore(volatile T& dest, U value) {
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__atomic_store_n(&dest, value, __ATOMIC_RELAXED);
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}
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template <typename T, typename U>
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inline void AtomicStoreRelease(volatile T& dest, U value) {
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__atomic_store_n(&dest, value, __ATOMIC_RELEASE);
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}
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template <typename T, typename U>
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inline T* AtomicExchangeAcquire(T* volatile& loc, U newval) {
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return __atomic_exchange_n(&loc, newval, __ATOMIC_ACQ_REL);
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}
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}
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@ -74,9 +92,9 @@ LONG SyncInterlockedIncrement(LONG *Dest)
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#else
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register int result;
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__asm__ __volatile__("lock; xadd %0,%1"
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: "=r" (result), "=m" (*Dest)
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: "0" (1), "m" (*Dest)
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: "memory");
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: "=r" (result), "=m" (*Dest)
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: "0" (1), "m" (*Dest)
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: "memory");
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return result;
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#endif
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}
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@ -88,9 +106,9 @@ LONG SyncInterlockedExchangeAdd(LONG *Dest, LONG Val)
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#else
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register int result;
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__asm__ __volatile__("lock; xadd %0,%1"
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: "=r" (result), "=m" (*Dest)
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: "0" (Val), "m" (*Dest)
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: "memory");
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: "=r" (result), "=m" (*Dest)
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: "0" (Val), "m" (*Dest)
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: "memory");
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return result;
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#endif
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}
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@ -102,9 +120,9 @@ LONG SyncInterlockedExchange(LONG *Dest, LONG Val)
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#else
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register int result;
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__asm__ __volatile__("lock; xchg %0,%1"
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: "=r" (result), "=m" (*Dest)
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: "0" (Val), "m" (*Dest)
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: "memory");
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: "=r" (result), "=m" (*Dest)
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: "0" (Val), "m" (*Dest)
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: "memory");
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return result;
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#endif
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}
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@ -31,7 +31,7 @@ namespace Common
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{
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inline void AtomicAdd(volatile u32& target, u32 value) {
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InterlockedExchangeAdd((volatile LONG*)&target, (LONG)value);
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_InterlockedExchangeAdd((volatile LONG*)&target, (LONG)value);
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}
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inline void AtomicAnd(volatile u32& target, u32 value) {
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@ -39,32 +39,43 @@ inline void AtomicAnd(volatile u32& target, u32 value) {
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}
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inline void AtomicIncrement(volatile u32& target) {
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InterlockedIncrement((volatile LONG*)&target);
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_InterlockedIncrement((volatile LONG*)&target);
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}
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inline void AtomicDecrement(volatile u32& target) {
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InterlockedDecrement((volatile LONG*)&target);
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}
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inline u32 AtomicLoad(volatile u32& src) {
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return src; // 32-bit reads are always atomic.
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}
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inline u32 AtomicLoadAcquire(volatile u32& src) {
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u32 result = src; // 32-bit reads are always atomic.
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_ReadBarrier(); // Compiler instruction only. x86 loads always have acquire semantics.
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return result;
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_InterlockedDecrement((volatile LONG*)&target);
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}
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inline void AtomicOr(volatile u32& target, u32 value) {
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_InterlockedOr((volatile LONG*)&target, (LONG)value);
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}
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inline void AtomicStore(volatile u32& dest, u32 value) {
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dest = value; // 32-bit writes are always atomic.
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template <typename T>
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inline T AtomicLoad(volatile T& src) {
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return src; // 32-bit reads are always atomic.
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}
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inline void AtomicStoreRelease(volatile u32& dest, u32 value) {
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template <typename T>
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inline T AtomicLoadAcquire(volatile T& src) {
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T result = src; // 32-bit reads are always atomic.
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_ReadBarrier(); // Compiler instruction only. x86 loads always have acquire semantics.
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return result;
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}
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template <typename T, typename U>
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inline void AtomicStore(volatile T& dest, U value) {
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dest = (T) value; // 32-bit writes are always atomic.
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}
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template <typename T, typename U>
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inline void AtomicStoreRelease(volatile T& dest, U value) {
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_WriteBarrier(); // Compiler instruction only. x86 stores always have release semantics.
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dest = value; // 32-bit writes are always atomic.
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dest = (T) value; // 32-bit writes are always atomic.
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}
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template <typename T, typename U>
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inline T* AtomicExchangeAcquire(T* volatile& loc, U newval) {
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return (T*) _InterlockedExchangePointer_acq((void* volatile*) &loc, (void*) newval);
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}
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}
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