JitArm64: Track singles in ps_sumX.
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@ -211,23 +211,29 @@ void JitArm64::ps_sumX(UGeckoInstruction inst)
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bool upper = inst.SUBOP5 == 11;
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ARM64Reg VA = fpr.R(a, REG_REG);
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ARM64Reg VB = fpr.R(b, REG_REG);
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ARM64Reg VC = fpr.R(c, REG_REG);
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ARM64Reg VD = fpr.RW(d, REG_REG);
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bool singles = fpr.IsSingle(a) && fpr.IsSingle(b) && fpr.IsSingle(c);
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RegType type = singles ? REG_REG_SINGLE : REG_REG;
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u8 size = singles ? 32 : 64;
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ARM64Reg (*reg_encoder)(ARM64Reg) = singles ? EncodeRegToDouble : EncodeRegToQuad;
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ARM64Reg VA = fpr.R(a, type);
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ARM64Reg VB = fpr.R(b, type);
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ARM64Reg VC = fpr.R(c, type);
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ARM64Reg VD = fpr.RW(d, type);
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.DUP(64, V0, upper ? VA : VB, upper ? 0 : 1);
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m_float_emit.DUP(size, reg_encoder(V0), reg_encoder(upper ? VA : VB), upper ? 0 : 1);
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if (d != c)
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{
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m_float_emit.FADD(64, VD, V0, upper ? VB : VA);
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m_float_emit.INS(64, VD, upper ? 0 : 1, VC, upper ? 0 : 1);
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m_float_emit.FADD(size, reg_encoder(VD), reg_encoder(V0), reg_encoder(upper ? VB : VA));
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m_float_emit.INS(size, VD, upper ? 0 : 1, VC, upper ? 0 : 1);
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}
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else
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{
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m_float_emit.FADD(64, V0, V0, upper ? VB : VA);
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m_float_emit.INS(64, VD, upper ? 1 : 0, V0, upper ? 1 : 0);
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m_float_emit.FADD(size, reg_encoder(V0), reg_encoder(V0), reg_encoder(upper ? VB : VA));
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m_float_emit.INS(size, VD, upper ? 1 : 0, V0, upper ? 1 : 0);
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}
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fpr.FixSinglePrecision(d);
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fpr.Unlock(V0);
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