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Fix a bit texture cache WIP for copyEFBToRam at least. 

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@1886 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
memberTwo.mb2 2009-01-17 13:31:17 +00:00
parent e3652c177c
commit 7f9ce70b33
1 changed files with 7 additions and 7 deletions
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12
Source/Plugins/Plugin_VideoOGL/Src/TextureMngr.cpp
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@ -231,10 +231,9 @@ TextureMngr::TCacheEntry* TextureMngr::Load(int texstage, u32 address, int width
* Metroids text issue (character table): * Metroids text issue (character table):
* Same addr, same GX_TF_C4 texture data but different TLUT (hence different outputs). * Same addr, same GX_TF_C4 texture data but different TLUT (hence different outputs).
* That's why we have to hash the TLUT too for TLUT format dependent textures (ie. GX_TF_C4, GX_TF_C8, GX_TF_C14X2). * That's why we have to hash the TLUT too for TLUT format dependent textures (ie. GX_TF_C4, GX_TF_C8, GX_TF_C14X2).
* And since the address and tex data don't change, the key index in the cacheEntry map can't be the address and * And since the address and tex data don't change, the key index in the cacheEntry map can't be the address but
* have to be a hash value (or address + few bits if address is really always aligned). This hash value takes count * have to be a real unique ID.
* of address, texture data @ address and if TLUT dependent fmt then the tlut @ tlutaddr. * DONE but not satifiying yet -> may break copyEFBToTexture sometimes.
* TODO: for small TLUT (ie. GX_TF_C4 => 16B) we have to hash on the whole TLUT because diff can be tiny.
* *
* Pokemon Colosseum text issue (plain text): * Pokemon Colosseum text issue (plain text):
* Use a GX_TF_I4 512x512 text-flush-texture at a const address. * Use a GX_TF_I4 512x512 text-flush-texture at a const address.
@ -265,8 +264,9 @@ TextureMngr::TCacheEntry* TextureMngr::Load(int texstage, u32 address, int width
if ( (format == GX_TF_C4) || (format == GX_TF_C8) || (format == GX_TF_C14X2) ) if ( (format == GX_TF_C4) || (format == GX_TF_C8) || (format == GX_TF_C14X2) )
{ {
// WARNING! texID != address now => may break CopyRenderTargetToTexture (cf. TODO up) // WARNING! texID != address now => may break CopyRenderTargetToTexture (cf. TODO up)
// tlut size (in bytes) mask can be up to 0x7FFF (GX_TF_C14X2) but Safer == Slower. // tlut size can be up to 32768B (GX_TF_C14X2) but Safer == Slower.
texID ^= TexDecoder_GetTlutHash(&texMem[tlutaddr], TexDecoder_GetPaletteSize(format)&0x7F); //texID ^= TexDecoder_GetTlutHash(&texMem[tlutaddr], TexDecoder_GetPaletteSize(format));
texID ^= TexDecoder_GetTlutHash(&texMem[tlutaddr], (format == GX_TF_C4) ? 32 : 128);
//DebugLog("addr: %08x | texID: %08x | texHash: %08x", address, texID, hash_value); //DebugLog("addr: %08x | texID: %08x | texHash: %08x", address, texID, hash_value);
} }
} }