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[ARM] Reenable ps_add. Issue is due to something in the FPR cache. Still needs to be investigated.

This commit is contained in:
Ryan Houdek 2013-09-04 03:27:45 +00:00
parent 8684b7635a
commit 7e26aace9f
1 changed files with 6 additions and 4 deletions
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8
Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Paired.cpp
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@ -27,14 +27,11 @@
#include "JitRegCache.h" #include "JitRegCache.h"
#include "JitAsm.h" #include "JitAsm.h"
// Wrong, THP videos like SMS and Ikaruga show artifacts
void JitArm::ps_add(UGeckoInstruction inst) void JitArm::ps_add(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(Paired) JITDISABLE(Paired)
Default(inst); return;
u32 a = inst.FA, b = inst.FB, d = inst.FD; u32 a = inst.FA, b = inst.FB, d = inst.FD;
if (inst.Rc){ if (inst.Rc){
Default(inst); return; Default(inst); return;
@ -48,6 +45,7 @@ void JitArm::ps_add(UGeckoInstruction inst)
VADD(vD0, vA0, vB0); VADD(vD0, vA0, vB0);
VADD(vD1, vA1, vB1); VADD(vD1, vA1, vB1);
fpr.Flush();
} }
// Wrong, THP videos like SMS and Ikaruga show artifacts // Wrong, THP videos like SMS and Ikaruga show artifacts
@ -106,6 +104,7 @@ void JitArm::ps_sum0(UGeckoInstruction inst)
VADD(vD0, vA0, vB1); VADD(vD0, vA0, vB1);
VMOV(vD1, vC1); VMOV(vD1, vC1);
fpr.Flush();
} }
void JitArm::ps_sub(UGeckoInstruction inst) void JitArm::ps_sub(UGeckoInstruction inst)
@ -126,12 +125,14 @@ void JitArm::ps_sub(UGeckoInstruction inst)
VSUB(vD0, vA0, vB0); VSUB(vD0, vA0, vB0);
VSUB(vD1, vA1, vB1); VSUB(vD1, vA1, vB1);
fpr.Flush();
} }
void JitArm::ps_mul(UGeckoInstruction inst) void JitArm::ps_mul(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(Paired) JITDISABLE(Paired)
u32 a = inst.FA, c = inst.FC, d = inst.FD; u32 a = inst.FA, c = inst.FC, d = inst.FD;
if (inst.Rc){ if (inst.Rc){
Default(inst); return; Default(inst); return;
@ -145,5 +146,6 @@ void JitArm::ps_mul(UGeckoInstruction inst)
VMUL(vD0, vA0, vC0); VMUL(vD0, vA0, vC0);
VMUL(vD1, vA1, vC1); VMUL(vD1, vA1, vC1);
fpr.Flush();
} }