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Merge pull request #249 from SeannyM/master 

(Rebase) Fixes two bugs in the ARM JIT core.
This commit is contained in:
Pierre Bourdon 2014-04-06 17:00:22 +02:00
parent b388123280 ccc4866118
commit 7d8604ac1c
3 changed files with 7 additions and 7 deletions
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2
Source/Core/Common/ArmEmitter.cpp
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@ -401,7 +401,7 @@ void ARMXEmitter::SetJumpTarget(FixupBranch const &branch)
_dbg_assert_msg_(DYNA_REC, distance > -0x2000000 && distance <= 0x2000000, _dbg_assert_msg_(DYNA_REC, distance > -0x2000000 && distance <= 0x2000000,
"SetJumpTarget out of range (%p calls %p)", code, branch.ptr); "SetJumpTarget out of range (%p calls %p)", code, branch.ptr);
u32 instr = (u32)(branch.condition | ((distance >> 2) & 0x00FFFFFF)); u32 instr = (u32)(branch.condition | ((distance >> 2) & 0x00FFFFFF));
instr |= branch.type ? /* B */ 0x0A000000 : /* BL */ 0x0B000000; instr |= (0 == branch.type) ? /* B */ 0x0A000000 : /* BL */ 0x0B000000;
*(u32*)branch.ptr = instr; *(u32*)branch.ptr = instr;
} }
void ARMXEmitter::B(const void *fnptr) void ARMXEmitter::B(const void *fnptr)

8
Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStore.cpp
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@ -19,7 +19,7 @@
void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset) void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset)
{ {
// All this gets replaced on backpatch // All this gets replaced on backpatch
Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK) Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
BIC(dest, dest, mask); // 1 BIC(dest, dest, mask); // 1
MOVI2R(R14, (u32)Memory::base, false); // 2-3 MOVI2R(R14, (u32)Memory::base, false); // 2-3
ADD(dest, dest, R14); // 4 ADD(dest, dest, R14); // 4
@ -212,7 +212,7 @@ void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offse
ADD(addr, addr, rA); // - 1 ADD(addr, addr, rA); // - 1
// All this gets replaced on backpatch // All this gets replaced on backpatch
Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK) Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
BIC(addr, addr, mask); // 1 BIC(addr, addr, mask); // 1
MOVI2R(rA, (u32)Memory::base, false); // 2-3 MOVI2R(rA, (u32)Memory::base, false); // 2-3
ADD(addr, addr, rA); // 4 ADD(addr, addr, rA); // 4
@ -461,7 +461,7 @@ void JitArm::lmw(UGeckoInstruction inst)
MOVI2R(rA, inst.SIMM_16); MOVI2R(rA, inst.SIMM_16);
if (a) if (a)
ADD(rA, rA, gpr.R(a)); ADD(rA, rA, gpr.R(a));
Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK) Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
BIC(rA, rA, mask); // 3 BIC(rA, rA, mask); // 3
MOVI2R(rB, (u32)Memory::base, false); // 4-5 MOVI2R(rB, (u32)Memory::base, false); // 4-5
ADD(rA, rA, rB); // 6 ADD(rA, rA, rB); // 6
@ -493,7 +493,7 @@ void JitArm::stmw(UGeckoInstruction inst)
MOVI2R(rA, inst.SIMM_16); MOVI2R(rA, inst.SIMM_16);
if (a) if (a)
ADD(rA, rA, gpr.R(a)); ADD(rA, rA, gpr.R(a));
Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK) Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
BIC(rA, rA, mask); // 3 BIC(rA, rA, mask); // 3
MOVI2R(rB, (u32)Memory::base, false); // 4-5 MOVI2R(rB, (u32)Memory::base, false); // 4-5
ADD(rA, rA, rB); // 6 ADD(rA, rA, rB); // 6

4
Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
View File

@ -129,7 +129,7 @@ void JitArm::lfXX(UGeckoInstruction inst)
if (Core::g_CoreStartupParameter.bFastmem) if (Core::g_CoreStartupParameter.bFastmem)
{ {
Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK) Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
BIC(rB, rB, mask); // 1 BIC(rB, rB, mask); // 1
MOVI2R(rA, (u32)Memory::base, false); // 2-3 MOVI2R(rA, (u32)Memory::base, false); // 2-3
ADD(rB, rB, rA); // 4 ADD(rB, rB, rA); // 4
@ -291,7 +291,7 @@ void JitArm::stfXX(UGeckoInstruction inst)
} }
if (Core::g_CoreStartupParameter.bFastmem) if (Core::g_CoreStartupParameter.bFastmem)
{ {
Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK) Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
BIC(rB, rB, mask); // 1 BIC(rB, rB, mask); // 1
MOVI2R(rA, (u32)Memory::base, false); // 2-3 MOVI2R(rA, (u32)Memory::base, false); // 2-3
ADD(rB, rB, rA); // 4 ADD(rB, rB, rA); // 4