Merge pull request #1174 from FioraAeterna/fifowriteaddrfix
JIT: properly remove FIFO write addresses when code is invalidated
This commit is contained in:
commit
7bce3fcdf9
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@ -66,7 +66,7 @@ void BreakPoints::Add(const TBreakPoint& bp)
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{
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m_BreakPoints.push_back(bp);
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if (jit)
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jit->GetBlockCache()->InvalidateICache(bp.iAddress, 4);
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jit->GetBlockCache()->InvalidateICache(bp.iAddress, 4, true);
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}
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}
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@ -82,7 +82,7 @@ void BreakPoints::Add(u32 em_address, bool temp)
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m_BreakPoints.push_back(pt);
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if (jit)
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jit->GetBlockCache()->InvalidateICache(em_address, 4);
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jit->GetBlockCache()->InvalidateICache(em_address, 4, true);
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}
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}
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@ -94,7 +94,7 @@ void BreakPoints::Remove(u32 em_address)
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{
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m_BreakPoints.erase(i);
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if (jit)
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jit->GetBlockCache()->InvalidateICache(em_address, 4);
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jit->GetBlockCache()->InvalidateICache(em_address, 4, true);
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return;
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}
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}
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@ -106,7 +106,7 @@ void BreakPoints::Clear()
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{
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for (const TBreakPoint& bp : m_BreakPoints)
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{
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jit->GetBlockCache()->InvalidateICache(bp.iAddress, 4);
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jit->GetBlockCache()->InvalidateICache(bp.iAddress, 4, true);
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}
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}
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@ -327,7 +327,7 @@ void Interpreter::dcbf(UGeckoInstruction _inst)
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NPC = PC + 12;
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}*/
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u32 address = Helper_Get_EA_X(_inst);
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JitInterface::InvalidateICache(address & ~0x1f, 32);
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JitInterface::InvalidateICache(address & ~0x1f, 32, false);
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}
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void Interpreter::dcbi(UGeckoInstruction _inst)
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@ -335,7 +335,7 @@ void Interpreter::dcbi(UGeckoInstruction _inst)
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// Removes a block from data cache. Since we don't emulate the data cache, we don't need to do anything to the data cache
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// However, we invalidate the jit block cache on dcbi
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u32 address = Helper_Get_EA_X(_inst);
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JitInterface::InvalidateICache(address & ~0x1f, 32);
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JitInterface::InvalidateICache(address & ~0x1f, 32, false);
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// The following detects a situation where the game is writing to the dcache at the address being DMA'd. As we do not
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// have dcache emulation, invalid data is being DMA'd causing audio glitches. The following code detects this and
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@ -359,7 +359,7 @@ void Interpreter::dcbst(UGeckoInstruction _inst)
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// Cache line flush. Since we don't emulate the data cache, we don't need to do anything.
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// Invalidate the jit block cache on dcbst in case new code has been loaded via the data cache
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u32 address = Helper_Get_EA_X(_inst);
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JitInterface::InvalidateICache(address & ~0x1f, 32);
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JitInterface::InvalidateICache(address & ~0x1f, 32, false);
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}
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void Interpreter::dcbt(UGeckoInstruction _inst)
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@ -159,7 +159,7 @@ bool Jit64::HandleFault(uintptr_t access_address, SContext* ctx)
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// CALLs, but we can't yet. Fake the downcount so we're forced to the
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// dispatcher (no block linking), and clear the cache so we're sent to
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// Jit. Yeah, it's kind of gross.
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GetBlockCache()->InvalidateICache(0, 0xffffffff);
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GetBlockCache()->InvalidateICache(0, 0xffffffff, true);
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CoreTiming::ForceExceptionCheck(0);
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m_clear_cache_asap = true;
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@ -327,7 +327,7 @@ using namespace Gen;
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WriteDestroyBlock(b.checkedEntry, b.originalAddress);
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}
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void JitBaseBlockCache::InvalidateICache(u32 address, const u32 length)
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void JitBaseBlockCache::InvalidateICache(u32 address, const u32 length, bool forced)
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{
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// Convert the logical address to a physical address for the block map
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u32 pAddr = address & 0x1FFFFFFF;
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@ -358,6 +358,16 @@ using namespace Gen;
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{
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block_map.erase(it1, it2);
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}
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// If the code was actually modified, we need to clear the relevant entries from the
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// FIFO write address cache, so we don't end up with FIFO checks in places they shouldn't
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// be (this can clobber flags, and thus break any optimization that relies on flags
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// being in the right place between instructions).
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if (!forced)
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{
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for (u32 i = address; i < address + length; i += 4)
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jit->js.fifoWriteAddresses.erase(i);
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}
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}
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}
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@ -161,7 +161,7 @@ public:
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CompiledCode GetCompiledCodeFromBlock(int block_num);
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// DOES NOT WORK CORRECTLY WITH INLINING
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void InvalidateICache(u32 address, const u32 length);
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void InvalidateICache(u32 address, const u32 length, bool forced);
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void DestroyBlock(int block_num, bool invalidate);
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};
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@ -210,10 +210,10 @@ namespace JitInterface
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jit->GetBlockCache()->Clear();
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}
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void InvalidateICache(u32 address, u32 size)
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void InvalidateICache(u32 address, u32 size, bool forced)
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{
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if (jit)
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jit->GetBlockCache()->InvalidateICache(address, size);
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jit->GetBlockCache()->InvalidateICache(address, size, forced);
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}
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u32 ReadOpcodeJIT(u32 _Address)
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@ -263,7 +263,7 @@ namespace JitInterface
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exception_addresses->insert(PC);
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// Invalidate the JIT block so that it gets recompiled with the external exception check included.
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jit->GetBlockCache()->InvalidateICache(PC, 4);
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jit->GetBlockCache()->InvalidateICache(PC, 4, true);
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}
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}
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}
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@ -36,7 +36,8 @@ namespace JitInterface
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void ClearSafe();
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void InvalidateICache(u32 address, u32 size);
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// If "forced" is true, a recompile is being requested on code that hasn't been modified.
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void InvalidateICache(u32 address, u32 size, bool forced);
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void CompileExceptionCheck(int type);
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@ -95,7 +95,7 @@ namespace PowerPC
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lookup_table[((tags[set][i] << 7) | set) & 0xfffff] = 0xff;
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}
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valid[set] = 0;
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JitInterface::InvalidateICache(addr & ~0x1f, 32);
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JitInterface::InvalidateICache(addr & ~0x1f, 32, false);
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}
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u32 InstructionCache::ReadInstruction(u32 addr)
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@ -288,7 +288,7 @@ void CCodeWindow::SingleStep()
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{
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if (CCPU::IsStepping())
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{
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JitInterface::InvalidateICache(PC, 4);
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JitInterface::InvalidateICache(PC, 4, true);
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CCPU::StepOpcode(&sync_event);
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wxThread::Sleep(20);
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// need a short wait here
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