DSPJitRegCache: Make the allocation array part of the DSPJitRegCache class
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@ -10,6 +10,12 @@
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using namespace Gen;
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// Ordered in order of prefered use.
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// Not all of these are actually available
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const std::array<X64Reg, 15> DSPJitRegCache::m_allocation_order = {{
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R8, R9, R10, R11, R12, R13, R14, R15, RSI, RDI, RBX, RCX, RDX, RAX, RBP
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}};
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static void* GetRegisterPointer(size_t reg)
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{
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switch (reg)
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@ -943,17 +949,11 @@ void DSPJitRegCache::WriteReg(int dreg, OpArg arg)
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PutReg(dreg, true);
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}
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//ordered in order of prefered use
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//not all of these are actually available
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static X64Reg alloc_order[] = {
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R8,R9,R10,R11,R12,R13,R14,R15,RSI,RDI,RBX,RCX,RDX,RAX,RBP
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};
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X64Reg DSPJitRegCache::SpillXReg()
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{
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int max_use_ctr_diff = 0;
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X64Reg least_recent_use_reg = INVALID_REG;
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for (X64Reg reg : alloc_order)
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for (X64Reg reg : m_allocation_order)
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{
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if (xregs[reg].guest_reg <= DSP_REG_MAX_MEM_BACKED &&
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!regs[xregs[reg].guest_reg].used)
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@ -974,7 +974,7 @@ X64Reg DSPJitRegCache::SpillXReg()
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}
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//just choose one.
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for (X64Reg reg : alloc_order)
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for (X64Reg reg : m_allocation_order)
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{
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if (xregs[reg].guest_reg <= DSP_REG_MAX_MEM_BACKED &&
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!regs[xregs[reg].guest_reg].used)
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@ -1007,13 +1007,14 @@ void DSPJitRegCache::SpillXReg(X64Reg reg)
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X64Reg DSPJitRegCache::FindFreeXReg()
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{
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for (X64Reg x : alloc_order)
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for (X64Reg x : m_allocation_order)
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{
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if (xregs[x].guest_reg == DSP_REG_NONE)
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{
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return x;
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}
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}
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return INVALID_REG;
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}
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@ -168,6 +168,8 @@ private:
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void MovToMemory(size_t reg);
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void FlushMemBackedRegs();
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static const std::array<Gen::X64Reg, 15> m_allocation_order;
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std::array<DynamicReg, 37> regs;
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std::array<X64CachedReg, 16> xregs;
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