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JitIL: Misc small optimizations.

This commit is contained in:
magumagu 2014-06-23 22:36:21 -07:00 committed by Pierre Bourdon
parent c8dd557dde
commit 79ecdf5fd0
1 changed files with 11 additions and 9 deletions
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20
Source/Core/Core/PowerPC/Jit64IL/IR_X86.cpp
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@ -763,9 +763,10 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
regMarkUse(RI, I, getOp1(getOp1(I)), 1); regMarkUse(RI, I, getOp1(getOp1(I)), 1);
break; break;
case BranchCond: { case BranchCond: {
if (isICmp(*getOp1(I)) && if (isICmp(*getOp1(I))) {
isImm(*getOp2(getOp1(I)))) {
regMarkUse(RI, I, getOp1(getOp1(I)), 1); regMarkUse(RI, I, getOp1(getOp1(I)), 1);
if (!isImm(*getOp2(getOp1(I))))
regMarkUse(RI, I, getOp2(getOp1(I)), 2);
} else { } else {
regMarkUse(RI, I, getOp1(I), 1); regMarkUse(RI, I, getOp1(I), 1);
} }
@ -861,9 +862,9 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
break; break;
} }
case StoreCR: { case StoreCR: {
Jit->MOV(64, R(RCX), regLocForInst(RI, getOp1(I))); X64Reg reg = regEnsureInReg(RI, getOp1(I));
unsigned ppcreg = *I >> 16; unsigned ppcreg = *I >> 16;
Jit->MOV(64, M(&PowerPC::ppcState.cr_val[ppcreg]), R(RCX)); Jit->MOV(64, M(&PowerPC::ppcState.cr_val[ppcreg]), R(reg));
regNormalRegClear(RI, I); regNormalRegClear(RI, I);
break; break;
} }
@ -1711,10 +1712,8 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
} }
case BranchCond: { case BranchCond: {
if (isICmp(*getOp1(I)) && if (isICmp(*getOp1(I))) {
isImm(*getOp2(getOp1(I)))) { regEmitCmp(RI, getOp1(I));
Jit->CMP(32, regLocForInst(RI, getOp1(getOp1(I))),
Imm32(RI.Build->GetImmValue(getOp2(getOp1(I)))));
CCFlags flag; CCFlags flag;
switch (getOpcode(*getOp1(I))) { switch (getOpcode(*getOp1(I))) {
case ICmpEq: flag = CC_NE; break; case ICmpEq: flag = CC_NE; break;
@ -1734,7 +1733,10 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
Jit->SetJumpTarget(cont); Jit->SetJumpTarget(cont);
if (RI.IInfo[I - RI.FirstI] & 4) if (RI.IInfo[I - RI.FirstI] & 4)
regClearInst(RI, getOp1(getOp1(I))); regClearInst(RI, getOp1(getOp1(I)));
} else { if (RI.IInfo[I - RI.FirstI] & 8)
regClearInst(RI, getOp2(getOp1(I)));
}
else {
Jit->CMP(32, regLocForInst(RI, getOp1(I)), Imm8(0)); Jit->CMP(32, regLocForInst(RI, getOp1(I)), Imm8(0));
FixupBranch cont = Jit->J_CC(CC_Z); FixupBranch cont = Jit->J_CC(CC_Z);
regWriteExit(RI, getOp2(I)); regWriteExit(RI, getOp2(I));