docs/DSP: Document rounding behavior of CLRL

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Pokechu22 2021-08-13 11:44:52 -07:00
parent 1bcea561e9
commit 79664d419c
1 changed files with 10 additions and 2 deletions

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@ -1736,14 +1736,22 @@ There are two pairs of conditions that work similarly: \texttt{EQ}/\texttt{NE} a
\end{DSPOpcodeFormat} \end{DSPOpcodeFormat}
\begin{DSPOpcodeDescription} \begin{DSPOpcodeDescription}
\item Clears \Register{\$acR.l} - low 16 bits of accumulator \Register{\$acR}. \item Rounds \Register{\$acR} such that \Register{\$acR.l} is 0. This is a round-to-even operation.
\end{DSPOpcodeDescription} \end{DSPOpcodeDescription}
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
$acR.l = 0 IF ($acR & 0x10000) != 0
$acR = ($acR + 0x8000) & ~0xffff
ELSE
$acR = ($acR + 0x7fff) & ~0xffff
ENDIF
FLAGS($acR) FLAGS($acR)
$pc++ $pc++
\end{DSPOpcodeOperation} \end{DSPOpcodeOperation}
\begin{DSPOpcodeNote}
\item An alternative interpretation is that if \Register{\$acR.m} is odd, then increment \Register{\$acsR} if \Register{\$acR.l} is greater than or equal to \Value{0x8000}; if \Register{\$acR.m} is even, then increment \Register{\$acsR} if \Register{\$acR.l} is greater than or equal to \Value{0x7fff}. Afterwards set \Register{\$acR.l} to 0.
\end{DSPOpcodeNote}
\end{DSPOpcode} \end{DSPOpcode}
\begin{DSPOpcode}{CLRP} \begin{DSPOpcode}{CLRP}