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Jit64: Use a temporary register for memory references. Part 1.

This commit is contained in:
degasus 2017-01-22 09:00:43 +01:00
parent 60d8ee4916
commit 78b36921d2
3 changed files with 6 additions and 4 deletions
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2
Source/Core/Core/HW/CPU.cpp
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@ -183,7 +183,7 @@ State GetState()
return s_state;
}
const volatile State* GetStatePtr()
const State* GetStatePtr()
{
return &s_state;
}

2
Source/Core/Core/HW/CPU.h
View File

@ -57,7 +57,7 @@ State GetState();
// Direct State Access (Raw pointer for embedding into JIT Blocks)
// Strictly read-only. A lock is required to change the value.
const volatile State* GetStatePtr();
const State* GetStatePtr();
// Locks the CPU Thread (waiting for it to become idle).
// While this lock is held, the CPU Thread will not perform any action so it is safe to access

6
Source/Core/Core/PowerPC/Jit64/Jit.cpp
View File

@ -780,7 +780,8 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer* code_buf, JitBloc
SetJumpTarget(extException);
TEST(32, PPCSTATE(msr), Imm32(0x0008000));
FixupBranch noExtIntEnable = J_CC(CC_Z, true);
TEST(32, M(&ProcessorInterface::m_InterruptCause),
MOV(64, R(RSCRATCH), ImmPtr(&ProcessorInterface::m_InterruptCause));
TEST(32, MatR(RSCRATCH),
Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN |
ProcessorInterface::INT_CAUSE_PE_FINISH));
FixupBranch noCPInt = J_CC(CC_Z, true);
@ -854,7 +855,8 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer* code_buf, JitBloc
ABI_PushRegistersAndAdjustStack({}, 0);
ABI_CallFunction(PowerPC::CheckBreakPoints);
ABI_PopRegistersAndAdjustStack({}, 0);
TEST(32, M(CPU::GetStatePtr()), Imm32(0xFFFFFFFF));
MOV(64, R(RSCRATCH), ImmPtr(CPU::GetStatePtr()));
TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF));
FixupBranch noBreakpoint = J_CC(CC_Z);
WriteExit(ops[i].address);