From de86d2003a20c547f0d03a2f29e1971f29811f89 Mon Sep 17 00:00:00 2001 From: Fiora Date: Mon, 15 Sep 2014 08:17:46 -0700 Subject: [PATCH] JIT: merge lbz + extsb PPC has no 8-bit sign-extended load, so this instruction pair is very common. x86 can do it in one op (movsx), so merge them when possible. --- Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp index e5ea85af01..9680a8439d 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp @@ -94,6 +94,15 @@ void Jit64::lXXx(UGeckoInstruction inst) PanicAlert("Invalid instruction"); } + // PowerPC has no 8-bit sign extended load, but x86 does, so merge extsb with the load if we find it. + if (accessSize == 8 && js.next_inst.OPCD == 31 && js.next_inst.SUBOP10 == 954 && + js.next_inst.RS == inst.RD && js.next_inst.RA == inst.RD && !js.next_inst.Rc) + { + js.downcountAmount++; + js.skipnext = true; + signExtend = true; + } + // TODO(ector): Make it dynamically enable/disable idle skipping where appropriate // Will give nice boost to dual core mode // (mb2): I agree,